Timing Requirements for Spallation Neutron Sources

1. Timing Requirements for Spallation Neutron Sources • Timing system clock synchronized to the storage ring’s revolution frequency. • LANSCE: 2.7951389 MHz (1/72 of the 201.25 MHz Acclerator RF frequency) • SNS: Variable. 1.027323 - 1.097502 MHz. Not derived from the Accelerator RF.

2. Timing Requirements for Spallation Neutron Sources • The end of the cycle is more important than the beginning of the cycle. • Large, high inertia, “T0” neutron choppers define when the beam is extracted from the ring. Most of the other important timing signals (beam and RF gates) end at the “Extraction Time” and derive their starting times by working backwards from the Extraction Time. • Multiple beam lines require multiple choppers to be synchronized by the timing system. • Compromise between keeping a stable “Extraction” reference signal for the choppers and not drifting too far away from the AC line phase for the RF system.

3. Basic Characteristics of SNS Timing System • Event System. • 256 events possible. 25 events currently in use. • ~5 millisecond machine cycle. 60 Hz. • Option to go to 120 Hz. when second target added. • 10 second super-cycle. • Clock synchronized with ring RF. • Ring RF is 1.057767 Mz at 1 GeV • Clock is 32 X Ring RF

4. GPS Timing System Components of SNS Timing System Event RTDL Link SNS Time Stamps Beam data Experimental Halls Master Timing IOC RF Gates Extraction Kickers TxHV Gates Timing SNS Real 10 MHz Slave Time Data Crystal (V124S) Link Osc. Master High resolution timestamps Machine Modes Machine SNS Event X32 PLL Protection Link (33 MHz) System Master Ring RF SNS Timestamps Remote Reset Synchronous ISR’s ICS IOC's Timing Reference Generator AC SNS Utility Module Line Beam Delay Beam Phase Micro pulse width Macro pulse width LEBT *4 PLL Chopper (64 MHz) Neutron Choppers SNS Time stamps Delays Gates Triggers Diagnostics Timing System Subsystem Hardware Hardware Timing System Users Experimental Systems

5. Two SNS Transmission Links • Event Link • Transmits the timing events that define a machine cycle. • Each event is 8 bits plus parity (256 events maximum). • Clock is variable and derived from the ring revolution frequency (32 * Frev). • Events 0 – 63 are generated by the timing system hardware. • Events 64 – 255 are generated by software (no fixed times). • Real-Time Data Link (RTDL) • Transmits machine parameters and data prior to every new cycle. • 128 frames possible (expandable to 255). • Each frame contains an 8-bit frame number, 24-bits of data, and an 8-bit CRC. • Clock is 10 MHz.

6. Sample SNS RTDL Data Frames Frame NumberData 1 – 3 Time of day 4 Event link period 5 MPS mode 6 60 Hz phase error 7 Beam Width 15 IOC Reset Address 17 Pulse Flavor 18-21 RF Gate Widths 24 Previous Pulse Status 25 Cycle 255 24-bit CRC (calculated)

7. SNS Machine Cycle Timeline Time Critical Events, (soft events disabled) Informational Events, non critical timing Real-Time Data Link(RTDL) RTDL parameter transmission(for next cycle) RTDLTransmit MPS FPL RF & High Voltage Events Extract MPS FPAR (Alternate) Cycle Start End Injection Snapshot, 1Hz, 6Hz, etc… Beam On System xxx Trigger Events Cycle Start Extraction Kicker Charge RTDL Valid Event Link Mostly Stable Triggers Beam On Range beam accumulation Allowed Range for Variable Triggers Anytime Machine Anytime Line-Synch Reference Clock -60 Hz ZeroCrossing +60 Hz ZeroCrossing 0 2 ms 4 ms 5 ms 6 ms 1 ms 3 ms 7 ms 8 ms

8. Basic Characteristics of LANSCE Timing System • “Gate” rather than “Event” driven system. • 96 independent timing gates  82 gates in use. • 8.3 millisecond machine cycle (120 Hz). • 1 second super-cycle. • Clock synchronized with ring RF. • 2.7951389 MHz.

9. Current Architecture of LANSCE Timing System Timing Gates • Star configuration • 4 redundant gate generator sets in 2 CAMAC crates. • Gate generators are loaded by Master Timer computer, then run independently. • Master Timer computer checks the output of the gate generators and automatically switches to another set when a discrepancy is seen. Timing Distribution Master Timer Timing Gate Generators MUX