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Computer Concept and Practice

Computer Concept and Practice. Basic Computer Architecture & Instruction Types. Basic Computer Architecture. Memory. CPU. 32bits. 000000···000. Registers. PC. Operation Unit (Arithmetic /Logic Unit : ALU). R0 R1 · · · R31. 4GB = 2 bytes. 32bits. 32. Memory

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Computer Concept and Practice

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  1. Computer Concept and Practice Basic Computer Architecture & Instruction Types

  2. Basic Computer Architecture Memory CPU 32bits 000000···000 Registers PC Operation Unit (Arithmetic /Logic Unit : ALU) R0 R1 · · · R31 4GB = 2 bytes 32bits 32 • Memory • Contains instructions and data • CPU • Repeat the following two steps 1) Fetch an instruction 2) Execute the instruction • Register • PC : indicates the memory address of the currently executing instruction • Others : "General Purpose" registers 111111···111 8bits

  3. OP OP OP OP Source Register 1 Source Register Register # Source Register Source Register 2 Constant Destination Register Destination Register Constant Register # OP OP Register #1 Destination Register Constant Register #2 Constant Register # (다) Store Instruction (Register -> Memory) (마) Jump Instruction (나) Load Instruction (Memory -> Register) (가)’ Arithmetic & Logic Instruction (라) Branch Instruction (가) Arithmetic & Logic Instruction Instruction Types 8bits 5bits 5bits 5bits 8bits 5bits 5bits 14bits 8bits 5bits 14bits 5bits 8bits 5bits 14bits 5bits 8bits 5bits 5bits 14bits 8bits 5bits

  4. ADD 00001 00010 00100 (가) Arithmetic & Logic Instruction Ex) ADD R1, R2, R4 OP Source Register 1 Source Register 2 Destination Register Arithmetic & Logic Instruction(1/2) 8bits 5bits 5bits 5bits Registers R0 + R1 R2 R3 R4 10 R5

  5. ADD’ 00100 00010 Ex) ADD’ R4, R2, 16 (가)’ Arithmetic & Logic Instruction OP Source Register Destination Register Constant Arithmetic & Logic Instruction(2/2) 8bits 5bits 5bits 14bits 00000000010000 Registers R0 + R1 R2 R3 R4 26 R5

  6. LOAD 00011 00000 (나) Load Instruction (Memory -> Register) Ex) LOAD R3, 4( R0 ) OP Destination Register Constant Register # Load Instruction 8bits 5bits 14bits 5bits 00000000000100 Memory 00···0000 Registers 00···0001 7 R0 00···0010 R1 00···0011 + R2 00···0100 R3 00···0101 13 R4 00···0110 13 R5 00···0111

  7. STORE 00100 00000 (다) Store Instruction (Register -> Memory) Ex) STORE R4, 0( R0 ) OP Source Register Constant Register # Store Instruction 8bits 5bits 14bits 5bits 00000000000000 Memory 00···0000 Registers 00···0001 7 10 R0 00···0010 R1 00···0011 + R2 00···0100 R3 00···0101 13 R4 00···0110 R5 00···0111

  8. BGE 00000 00010 (라) Branch Instruction Ex1) BGE R0, R2, 12 OP Register #1 Register #2 Constant Branch Instruction(1/2) 8bits 5bits 5bits 14bits Memory A 00000000001100 A+1 A+2 A+3 R0 A+4 4 PC >=? A+5 R1 A+6 R2 A+7 R3 A+8 + R4 A+9 R5 A+10 A+11 Registers

  9. BGE 00000 00010 (라) Branch Instruction Ex1) BGE R0, R2, 12 OP Register #1 Register #2 Constant Branch Instruction(1/2) 8bits 5bits 5bits 14bits Memory A 00000000001100 A+1 A+2 A+3 R0 A+4 4 PC >=? A+5 R1 A+6 R2 A+7 R3 A+8 + R4 A+9 R5 A+10 A+11 Registers

  10. BLE 00000 00011 (라) Branch Instruction Ex2) BLE R0, R3, 20 OP Register #1 Register #2 Constant Branch Instruction(2/2) 8bits 5bits 5bits 14bits Memory A 00000000010100 A+1 A+2 A+3 R0 A+4 4 PC A+5 <=? R1 A+6 R2 A+7 R3 A+8 + R4 A+9 R5 A+10 A+11 Registers

  11. BLE 00000 00011 (라) Branch Instruction Ex2) BLE R0, R3, 20 OP Register #1 Register #2 Constant Branch Instruction(2/2) 8bits 5bits 5bits 14bits Memory A 00000000010100 A+1 A+2 A+3 R0 A+4 4 PC A+5 <=? R1 A+6 R2 A+7 R3 A+8 + R4 A+9 R5 A+10 A+11 Registers

  12. JUMP 00010 (마) Jump Instruction Ex) JUMP R2 OP Register # Jump Instruction 8bits 5bits Memory 20 21 Registers 22 R0 23 PC R1 R2 A+24 R3 A+25 R4 A+26 R5 A+27

  13. JUMP 00010 (마) Jump Instruction Ex) JUMP R2 OP Register # Jump Instruction 8bits 5bits Memory 20 21 Registers 22 R0 23 PC R1 R2 A+24 R3 A+25 R4 A+26 R5 A+27

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