Early Validation of MPSoCs Thermal Mitigation through Integration of Thermal Simulation in SystemC Virtual Prototypi

1. Early Validation of MPSoCs Thermal Mitigation through Integration of Thermal Simulation in SystemC Virtual Prototyping Tanguy Sassolas1, Charly Bechara1, Pascal Vivet2, Hela Boussetta3 & Luca Ferro3 Pascal.Vivet@cea.fr CEA List1,CEA Leti2, Docea Power3

2. Thermal issues in modern SoCs • Increasing thermal issues • Technology scaling => higher power density • 3D stacking with TSV => greater thermal issues • Temperature impacts • Power consumption • Peak performance • Ageing • Package costs • MPSoCarchitectures • Dynamic applications, variable execution time • Power management solutions (DVFS), can even worsen thermal properties!  Thermal mitigation schemes must be proposed at design time

3. Thermal design flow 12 -24 months 2-3 months 6 months • Need for thermal evaluation tools that take into account a complete SoC environment and its dynamic behaviour • Need early HW/SW thermal effects evaluation => ESL • Linking thermal/power/functional tools in the same design flow is mandatory High level model (e.g. systemC) Area & power consumption chip New architecture concept Fixed floorplan constraints RTL model sales netlist Tape out Floorplan exploration Fab Architecture exploration VHDL design Synthesis Refined Power Studies Place & Route w. Thermal sign off Circuit test Development & Validation Online thermal control Early power evaluation

4. Thermal Simulation State of the art • Low level tools: Multiphysics simulation • Multiphysics level : FloTherm(Mentor Graphics), Icepak (Ansys/Apache), … • Mostly oriented to package/board and active cooling (fan) design • Post-layout level : Heatwave (Gradient DA) • Adapted to short term analysis at die level but long simulation times • Fine grain but not adapted to SoC/Platform level exploration • High level tools: • HotSpot: Complex grid, long transient simulation • 3D-ICE: Built for 3D stacks, little packaging description • Mostly academic tools • No native evaluation of thermal impact on power nor link with VP • Existing Virtual Platforms (SystemC/TLM) • May include power models but no thermal models No Thermal/Power/Functional ESL frameworkfor early design

5. Thermal ESL Modeling & Simulation Framework Power AceplorerTM (Power modeling and coupled Power/Thermal simulation) Functional AceTLMConnectTM (Library for functional, power, thermal parametermonitoring & providingco-simulation link) AceThermalModelerTM (DynamicCompact Thermal Model) Functional  : Activity, BW, ... Thermal values Power & Thermal values / TLM

6. MPSoCuse case: LOCOMOTIV • LOCOMOTIV architecture • Multi-Core with shared memory • Thermal sensors • Power management • Local: adapts to process/ageing/temperature • Global: DVFS control per core • Hardware AssistedRuntime Software (HARS) • Pedestrian Detection Application • Variable execution time • Parallelexecution

7. Power & Thermal Aware Virtual Platform ExistingVirtual Platform Power Thermal Application Application Power actuator Runtimesync Runtime Thermal management Hardware dependent SW Sync HAL Thermal sensor HAL DVFS HAL Timed HW platform or PVT platform ISS & HW blocks Thermal sensor Power unit AceTLMConnect Clockdomain & voltage supply activity Power & thermal analysistools Static & Dynamic power Temperature

8. LOCOMOTIV : Power Modeling • Aceplorer power model • 5 DPM modes (Idle 0, Idle 1, Idle 2, Idle 3, NoFetch) • 5 frequencies (500 Mhz, 375 Mhz, 187.5Mhz, 68.75Mhz, 0Mhz) • 1 generic frequency mode (Vdd-Hopping) • Power values refined from post layout simulations • Full temperature impact is characterized • Impact on leakage • Impact on dynamic consumption DVFS modes DPM modes Vddhopping mode

9. LOCOMOTIV : Thermal Modeling • Thermal description withAceThermalModeler • Model geometries and materialproperties • Generate a Compact Thermal model • Die model according to floorplan • SBGA304 package (5.08x5.08 mm) • PCB model (4 dies, 1 FPGA) • Thermal sensors • Real Thermal Sensorbuilt of Ring Oscillators • Sensortemperatureprovided by Aceplorer • Thermal values accessedthroughruntime HAL [L. Vincent, DAC’12]

10. Online thermal management • Software stackenhancedwith thermal control • Cooperativeruntime(Threads queue handed by master core) • Schedule power hungrytasks to lowtemperaturecores • Reactive thermal control: AdaptDVFS to meet thermal budget • Profit from data dependant computation to reduce PE performances • SlackReclamation + Idle mode whenreachingtemperaturethreshold • SlackReclamationwithTemperatureThresholds : • If t > WCET & Temp < Thigh, thenDVFS + • If t < WCET, then DVFS - • If t > Tframe, thenloosenext frame • If Temp > Tcrit., go to IDLE mode • If Temp < Tlow, startnext frame

11. Thermal management results (1/3) No thermal mitigation Fast Simulation of Temperature Warm-up phase (Simulators are decoupled) Thermal budget iscrossed : T > 95 °C Peaktemperature = 114°C Thermal control isneeded Tools are mandatory for early exploration and validation

12. Thermal management results (2/3) No thermal mitigation Idle Time Management + Thresholds Thermal budget isrespected: T < 95°C Usingthresholds : 70°C < T < 90 °C Peaktemperature = 90,71°C Thermal control works but withpoor application results : Skipped frames : 10/52 but successive frames !

13. Thermal management results (3/3) No thermal mitigation Idle Time Management + Thresholds SlackReclamation + Thresholds Slackreclamation Fine grain power and thermal analysis simulation time: 16 minutes (SystemC VP simulation time only : 5 minutes) Compliantwithearly design phases! Thermal budget respected : T < 95°C, samethresholds: 70°C < T < 90 °C Peaktemperature = 91,2°C Slackreclamation : use estimatedremaining time to reduceDVFS Skipped frames : 3/52. Application renderingispreserved.

14. Conclusion • Validated thermal mitigation algorithm • Thermal mitigation isbecomingmandatorywith power & thermal issues • Thermal/Power/Functional ESL design flow demonstrated • with a MPSoC architecture on a real video application • Limited developmentcosts • Power & Thermal modelling : using commercial ESL tools (Aceplorer & ATM) • Can beeasilyconnected to standard Virtual Platforms (SystemC/TLM) • Limited simulation costs, using compact transient thermal models • Perspectives • More advanced (predictive) thermal mitigation algorithm • Confrontation of the design flow withLOCOMOTIV siliconresults

15. Thank you for your attention. Any Questions ??? • Come and Discussaround the poster • Come and See the demo @ DOCEA’sbooth, • exhibitor 2113