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Technological Aspect of the Trigger-Less Readout Architecture for the LHCb Upgrade at CERN

Technological Aspect of the Trigger-Less Readout Architecture for the LHCb Upgrade at CERN. Topical Workshop on Electronics for Particle Physics (IEEE 2013) 2013 October 27 - November 2 Seoul, Korea. Guillaume Vouters LAPP - Annecy - France on behalf of the LHCb Collaboration.

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Technological Aspect of the Trigger-Less Readout Architecture for the LHCb Upgrade at CERN

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  1. Technological Aspect of the Trigger-Less Readout Architecture for the LHCb Upgrade at CERN Topical Workshop on Electronics for Particle Physics (IEEE 2013) 2013 October 27 - November 2 Seoul, Korea Guillaume VoutersLAPP - Annecy - France on behalf of the LHCb Collaboration

  2. Outline • Introduction to LHCband current performance • Motivationsfor an upgradeof the LHCb detector • Current limitations • Detector Upgrade • Readout Architecture Upgrade • FE Trigger-less electronics • DAQ technologies • Firmware architecture • Outlook onplansand futurerunning conditions Guillaume Vouters - IEEE 2013, Seoul, Korea

  3. Current LHCb detector First-level HW trigger Calorimeters Muon Particle ID Vertexing Tracking Guillaume Vouters - IEEE 2013, Seoul, Korea

  4. Upgrading LHCb • The amount of data and the physics yield from data recorded by the current LHCb experiment is limited by its detector, readout technologies and hardware trigger. • While LHC accelerator will keep steadily increasing … • energy / beam (3.5  4  6.5 TeV  …) • luminosity(peak 8x1033  2x1034cm-2s-1 … ) • … LHCb will stay limited in terms of • data bandwidth: limited to 1.1 MHz / 40 MHz max • physics yields for hadronic channels at the hardware trigger • detectors degradationat higher luminosities Now! Design! Guillaume Vouters - IEEE 2013, Seoul, Korea

  5. Upgrade Strategy Remove first-level hardware trigger!  accept all LHC bunch crossing: trigger-less Front-End electronics Readout Supervisor L0 Hardware Trigger Current HLT ~1Tb/s 1MHz eventrate Readout Supervisor Low-level Trigger Upgrade HLT++ Low-level Trigger ~40 Tb/s Courtesy K. Wyllie 40MHzeventrate Guillaume Vouters - IEEE 2013, Seoul, Korea

  6. Trigger-less FE NO TRIGGER to FE!  Only commands, clock and slow control • Compress (zero-suppress) data already at the FE • reduce # of links from ~80000 to ~12500 (~20 MCHF to ~3.1 MCHF) • data driven readout (asynchronous) + variable latencies! • Efficiently usage of link bandwidth for data • pack data on data link continuously with elastic buffer • extensive use of CERN GBT (robust FEC or WideBus mode) • evaluate choices based on complexity vsrobustness Guillaume Vouters - IEEE 2013, Seoul, Korea

  7. Efficient Data Packing Mechanism Average event size = link bandwidth Link bandwidth Average event size 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 = + Buffer depth • Header is the unique identifier for each event in frame • Compulsory (tag for each LHC crossing) • Programmable in its content (must contain length of frame and BXID) • Used by readout board to decode and separate frames BX0 BX0 BX1 BX1  BX2 BX2 BX BX3 3 BX4 BX4 Guillaume Vouters - IEEE 2013, Seoul, Korea

  8. Calorimeters Reduce PMT gain + new electronics Particle ID Replace HPDs + electronics Upgraded LHCb Detector Muon newelectronics New Vertex Detector New Tracking stations Guillaume Vouters - IEEE 2013, Seoul, Korea

  9. LHCb Upgrade Readout Architecture Replicate for as much as needed (scalable) Same ATCA board used in different flavors: same generic hardware, different firmware Guillaume Vouters - IEEE 2013, Seoul, Korea

  10. Back-End: New LHCb readout board Classical approach: ~0.5 Tb/s data aggregator board with 10 GbE to FARM 24 inputs @ 4.8 Gb GBT format 12 outputs/ inputs @ 10Gb ethernet AMC 96 inputs @ 4.8 Gb  processing in FPGA  48 x 10G ethernet ports Guillaume Vouters - IEEE 2013, Seoul, Korea

  11. ATCA40 Under test Guillaume Vouters - IEEE 2013, Seoul, Korea

  12. AMC40 • TELL40 = ATCA40 + 4xAMC40 • + specific TELL40 firmware in AMC40 Nowready and beingtested! Guillaume Vouters - IEEE 2013, Seoul, Korea

  13. Common Firmware Development SOL 40 FE(s) data (up to 24) Low Level Interface Common development TFC command decoder Throttle Specific development Throttle resets If 80 bits width GBT x6 x6 Memory x6 ErrorRecovering x6 If 112bits width GBT MEP building DataProcessing LLT decision x6 BCIDAlignment Decoding ECS Low Level Interface Computer Network DDR3 CCPC Guillaume Vouters - IEEE 2013, Seoul, Korea

  14. AMC40 test setup (MiniDAQ) • The MiniDAQ is the first step to the LHCb DAQ upgrade in order to check : • Hardware functionalities • Firmware developments • Software developments Guillaume Vouters - IEEE 2013, Seoul, Korea

  15. LHCb data taking plan Tendering & Serial production Installation & commissioning upgrade (18 months to plan!) Upgrade TDRs Quality control & acceptance tests 2014 2017 2016 2015 2019 2018 2020 2022 2021 LHC LSI LHC LSII LHC Run II LHC LSIII LHC Run III Technical reviews & technology choices (ongoing now!) for high-lumi LHC Lpeak> 5x1034cm-2s-1 Guillaume Vouters - IEEE 2013, Seoul, Korea

  16. Conclusion • An upgrade plan of the LHCb experiment has been laid out • Aim at collecting10x more data and 20x more hadronic events • LHCb upgrade istechnologically challenging and time wise tight • Trigger-less, ~40 Tb/s network, minimize number of components • Optimize costs and manpower: be smarter … • R&D, specs, evaluation, validation are ongoing. • CERN endorsed the LHCb Upgrade by fully approving it! • We have exciting times ahead in 2014 and beyond! Guillaume Vouters - IEEE 2013, Seoul, Korea

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