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A N DY Trigger/DAQ and Electronics

A N DY Trigger/DAQ and Electronics. Chris Perkins UC Berkeley/Space Sciences Laboratory Stony Brook University. A N DY Review. 03/30/2012. Trigger/DAQ Design. RHIC Crossing Rate : 10 MHz Hadronic Interaction Cross Section : ~30 mb

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A N DY Trigger/DAQ and Electronics

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  1. ANDYTrigger/DAQ and Electronics Chris Perkins UC Berkeley/Space Sciences Laboratory Stony Brook University ANDY Review 03/30/2012

  2. Trigger/DAQ Design • RHIC Crossing Rate : 10 MHz • Hadronic Interaction Cross Section : ~30 mb • Drell-Yan Signal Cross Section : ~7 x 10-5mb at 500GeV • Need reconfigurable Digital Trigger System/Pattern Recognition to distinguish signal from other interactions • Most of Trigger System uses charge integration of PMT type signals • Beam-Beam Counters (BBC) and part of Preshower (PS-IC) need relatively crude timing resolution of hits for basic Minimum Bias Trigger • Trigger System is a tree of custom built electronics • Overall design of ANDY Trigger/DAQ system was ported from STAR Experiment Trigger System Portion of STAR Trigger Tree ANDY Trigger Tree – Run 2011 Chris Perkins

  3. DAQ Dataflow • Event Readout rate up to ~4 kHz depending on detector occupancy • Nearly zero deadtime • Token indexing system correlates packets from each crate and assembles into full event • All electronics kept in sync using custom designed RHIC Clock and Control (RCC) Board • Additional VME crates/Trigger boards can be added to system with no penalty because VME crates readout in parallel Chris Perkins

  4. Trigger and DAQ System Overview All Custom Designed and Built Electronics Digitization, Buffering, Preliminary Trigger Algorithms DAQ Receiver (Linux) Custom Data Network Start/Stop Data Taking Triggering Chris Perkins

  5. Trigger Boards • Digitizes Analog PMT Input Signals • Buffers incoming data • Performs initial Trigger Algorithm on data • Trigger data Read out over VME • Onboard Memory: Enough to store 7ms worth of data • Low Noise: RMS Pedestal variation < 1 count QT Boards : DSM Boards : • 32 Analog Input channels • 32 Digital Output bits • To Trigger Tree • 32 Discriminator Outputs • For timing triggers • Programmable FPGA over VME • For Trigger algorithms • 128 Digital Input bits • Differential Signaling • From QT or DSM • 16 channels x 8 bits • 32 Digital Output bits • Programmable FPGA over VME • For Trigger Algorithms • Buffered data Read out over VME • Performs Trigger Algorithmon 128 input bits to produce 32 output bits for next layer of trigger tree Chris Perkins

  6. Trigger Electronics Tree – Run 2011 • Digitizers/Buffering/Data Manipulation • Digital Trigger Tree • Data funnels through digital electronics • tree with algorithms performed at • each level • Last board in tree makes final decision • whether or not to trigger and readout • data • Trigger algorithms in FPGAs for easily • reconfigurable triggers (over VME) • Trigger system can look at every RHIC • crossing for a trigger (10 MHz) • (zero deadtime) Chris Perkins

  7. Detector Diagram – Run 2012 • Test GEM Trackers using independent Scalable Readout System (SRS) • No Changes to Trigger Tree from Run 2011 • Add 20 HCal Modules to close gap above and below beam pipe • Signals will fit into existing HCal QT Boards Chris Perkins

  8. Detector Diagram – Run 2013 • No BBC-Blue • Add new PreShower (PS) • Add New ECal • Old PreShower -> Midη • Old ECal -> FPDY • Expanded HCal • Add first GEM tracking station • Triggered from AnDY Trigger System • Readout using “Scalable Readout System” (SRS) • Data Acquisition independent from rest of AnDY DAQ system Chris Perkins

  9. Trigger Electronics Tree – Run 2013 • No BBC-Blue • (-1 QT, -1 TAC) • Add new PreShower (PS) • (+10 QT, +4 TAC) • Add New ECal • (+50 QT, +5 DSM) • Old PreShower -> Mid η • (+4 QT, +6 TAC) • Old ECal -> FPDY • Expanded HCal • (+2 QT) Chris Perkins

  10. Scalable Readout System (SRS) • Readout System for GEM Tracking Stations • Triggered from AnDY Trigger System Slide from talk by MarcinByszewski Chris Perkins

  11. Detector Diagram – Run 2014 • Add Magnet and Second/Third Tracking Stations • No Change to Trigger Tree from Run 2013 Chris Perkins

  12. Trigger VME Crate Layout – 2011/2012 • 3 Total VME Crates • Same in 2011 and 2012 Chris Perkins

  13. Trigger VME Crate Layout – Run 2013/2014 • 10 Total VME Crates will fit into existing STP Data Network • Crates readout in parallel so same DAQ rate capabilities • Same in 2013 and 2014 Chris Perkins

  14. Reconfigurable FPGA Trigger Algorithms • The following triggers have been developed so far and can be interleaved with each other during data-taking: • LED (for monitoring detector stability/gains) • Cosmic-rays (for relative calibration of Hcal) • Minimum-bias (based on BBC) • ECal Sum (for triggering on π0) • HCal Sum (for triggering on jets) • ZDC (for local polarimetry) Chris Perkins

  15. Trigger Commissioning Timeline – Run 2011 • 26 Jan – First Collisions at AnDY • Initial Minimum Bias Trigger Commissioning • 27 Jan– Further Minimum Bias TrgCommissioning • 28 Jan– 29 Jan– No Beam • 30 Jan– Final Minimum Bias TrgCommissioning • 31 Jan–01 Feb– No Beam • 02 Feb– Minimum Bias Trigger Production Mode • 12 Feb–“Physics Running” Declared at RHIC • Jet Trigger (HCalSum) Commissioned and Production Running • 01 Mar–π0Trigger (ECalSum) Commissioned Chris Perkins

  16. Trigger Data Flow – Minimum Bias Trigger • Used in Run 11 Chris Perkins

  17. Trigger Data Flow – ECal High-Tower Trigger • For Full ECal in Run 13 Chris Perkins

  18. Jet Trigger • Jet Trigger = Threshold on HCal Sum with BBC collisionrequirement • Crossings before and after Jet trigger are relatively clean • Delivered luminosity is fully recorded, with minimal impact from livetime Chris Perkins

  19. Example : Jet Triggered Events • Select from jet-trigger events for HCal “high-tower” to be centered in module • Display for each detector of each module the ADC count as color scale (black=greatest count yellow=lowest count) • Events look “jetty”, as expected Chris Perkins

  20. Conclusions • STAR Trigger System Infrastructure Design was successfully ported to AnDY Trigger/DAQ System for Run 2011 • A suite of simultaneously running triggers was developed and used in 2011 • Expanded detector set in future runs will fit into current Trigger/DAQ system while retaining current DAQ rate capabilities • Run 2011 Commissioning experience shows that new detectors and triggers can be commissioned very quickly once collisions are established Chris Perkins

  21. Backup Slides Chris Perkins

  22. ANDY Experimental SetupRHIC Run 2011 ZDC-Yellow ZDC-Blue BBC-Yellow Chris Perkins

  23. ANDY in January, 2011 Trigger/DAQ electronics Left/right symmetric HCal Left/right symmetric ECal Blue-facing BBC Left/right symmetric preshower Beryllium vacuum pipe Chris Perkins

  24. Digitizing, Buffering, and Trigger Algorithm Boards QT Boards : • 32 Analog Input channels • 32 Digital Output bits • To Trigger Tree • 32 Discriminator Outputs • For timing triggers • Programmable FPGA over VME • For Trigger algorithms • Digitizes Analog PMT Input Signals • Buffers incoming data • Performs initial Trigger Algorithm on data • Trigger data Read out over VME • Onboard Memory: Enough to store 7ms worth of data • Low Noise: RMS Pedestal variation < 1 count Chris Perkins

  25. QT Boards (Continued) • Custom designed charge integrator circuit for PMT input signals • 12-bit, 70 MSPS Analog-to-digital converters • Configuration programmable over VME: • Daughterboard FPGAs (containing trigger algorithms) • Digitizer Gate Start/Stop (1 ns steps) • Discriminator Thresholds • Dynamic range and sensitivity: • 0-200 GeV, ~0.05 Gev (12 bit dynamic range) • ~ 0.25 pC/count ADC • Linearity over the full range • Active Capture Time: ~85ns per crossing (~85%) Motherboard Datapath Daughterboard Datapath Chris Perkins

  26. Data Storage and Manipulation (DSM) Boards • 128 Digital Input bits • Differential Signaling • From QT or DSM • 16 channels x 8 bits • 32 Digital Output bits • Programmable FPGA over VME • For Trigger Algorithms • Buffered data readout over VME • Performs trigger algorithm on 128 input bits to produce 32 output bits for next layer of trigger tree DSM Datapath Chris Perkins

  27. Clock Distribution • Need to keep all boards in sync across many VME crates • Custom designed RHIC Clock and Control (RCC) Board • Buffers incoming clock from accelerator (~ 10 MHz) • Fans out clock and control signals to individual trigger boards and digitizer board VME crates • Configurable phase controls Chris Perkins

  28. Data Acquisition Receiver • Individual boards in each VME crate are readout over the VME backplane • Data is sent to an aggregating DAQ receiver over a custom built Fiber Data Network (overall data rate ~ 2 Gb/s) • Standard Linux machine (DAQ) houses custom built PCI card to receive digitized and triggered data • Current bottleneck is boards readout serially over VME backplane • Additional VME crates/Trigger boards can be added to system with no penalty because VME crates readout in parallel • Events can currently be collected at ~ 4kHz depending on detector occupancy • Further optimization is still ongoing • Token indexing system correlates packets from each crate and assembles into full event Chris Perkins

  29. Scaler Boards • Capable of capturing input bits for every RHIC crossing (~10 MHz) • Currently 32 input bits but easily expandable in the future • Data is streamed to Linux Data Receivers and stored on disk Top Bottom Chris Perkins

  30. Trigger Crate Layout – Run 2012 • Same as Run 2011 Chris Perkins

  31. Trigger Crate Layout – Run 2014 • Same as Run 2013 until Tracking design is finalized Chris Perkins

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