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DØ Silicon Microstrip Tracker for runIIa

DØSMT. DØ Silicon Microstrip Tracker for runIIa. Design Production Assembly Readout Installation Commissioning Conclusions. Eric Kajfasz (CPPM/FNAL) - Breese Quinn (FNAL) Como, October 15, 2001 presented by Alice Bean (Kansas/FNAL). RunIIa SMT Design. 12 F Disks.

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DØ Silicon Microstrip Tracker for runIIa

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  1. DØSMT DØ Silicon Microstrip Tracker for runIIa • Design • Production • Assembly • Readout • Installation • Commissioning • Conclusions Eric Kajfasz (CPPM/FNAL) - Breese Quinn (FNAL) Como, October 15, 2001 presented by Alice Bean (Kansas/FNAL)

  2. RunIIa SMT Design 12 F Disks 4-layer barrel cross-section 4 H Disks 6 Barrels SMT Statistics 72 ladders 12 cm long 6192 R/O chips = 792,576 channels > 1.5 million wire bonds E. Kajfasz/B. Quinn

  3. RunIIa SMT Design E. Kajfasz/B. Quinn

  4. SVXIIE chips 9-chip HDI for 20 sensor Bus control and power traces Be substrate High Density Interconnect • Kapton based flex circuits with0.2 mm pitch for chip mounting • Laminated to Beryllium substrateand glued to Silicon sensor • Connects Sensor to SVXII chips and SVXII chips to flex circuit via wire bonds(Al wedge bonding) • Connects to a Low Mass Cable which carries the signals out of the interaction region E. Kajfasz/B. Quinn

  5. SVXIIFE SVXIIBE Pipeline Control Logic I/O Analog Pipeline To Silicon Detector To Readout System 128 channels Sparsification FIFO ADC Comparators Integrators (128 channels) ADC ramp and counter 32 storage cells/channel Analog section Digital section SVXIIe chip • 1.2 um CMOS amplifier/analog delay/ADC chip fabricated in the UTMC rad hard process • Designed by LBL/FNAL • Some features: • 128 channels • 32 cell pipeline/channel • 8-bit Wilkinson ADC • Sparsification • 53 MHz readout • 106 MHz digitization • 6.4 x 9.7 mm2 • About 85,000 transistors E. Kajfasz/B. Quinn

  6. SVXIIe chip Externally programmed to achieve optimal performance for 132 or 396ns beam crossings and detector capacitances from 10 to 35pF (preamp bandwidth adjustment) Chip noise490e + 50e/pFi.e. ~1200e ENC for C=15pF1 MIP => ~4fC => ~25,000e=> S/N ~ 20 Max dealy in analog pipeline:32 x 132ns = 4.2us E. Kajfasz/B. Quinn

  7. Production: 3-chip ladders • 72 single-sided axial ladders • 2 sensors/ladder • Located on 1st and 3rd layer of 2 outer barrels • Be substrate, HDI and rohacell foam/carbon fiber rails glued on Silicon sensor E. Kajfasz/B. Quinn

  8. Production: 6-chip ladders N-side P-side • 144 double-sided double-metal axial/90° ladders • 1 sensor/ladder • Located on 1st and 3rd layer of 4 inner barrels Be substrate, HDI and rohacell foam/carbon fiber rails glued on Silicon sensor E. Kajfasz/B. Quinn

  9. Production: 9-chip ladders N-side P-side • 216 double-sided axial/2° ladders • 2 sensors/ladder • Located on 2nd and 4th layer all 6 barrels Be substrate, HDI and rohacell foam/carbon fiber rails glued on Silicon sensor E. Kajfasz/B. Quinn

  10. Production: F-wedges N-side P-side Silicon sensor glued on HDI • 144 double-sided ±15° strips • 6 (n) and 8 (p) readout chips • 1 sensor/wedge • Located on 12 F-disks E. Kajfasz/B. Quinn

  11. Production: H-wedges • 96x2 back to back single-sided, ±7.5° strip angles • 6-chip readout per side • 2 sensors/wedge • Be substrate and HDI glued on Silicon sensor • Located on 4 H-disks E. Kajfasz/B. Quinn

  12. Production: Sensor problems • Sensor lithography defects • A silicon manufacturing problem produced p-stop isolation defects in the 90° stereo ladders. This resulted in a 30% yield from the manufacturer. • Micro-discharge effect • With negative p-side bias on double-sided detectors, we observed micro- discharges producing large leakage currents and noise above a certain breakdown voltage. • The effect occurs along the edges of the p implants, where large field distortions and charge accumulations result from misalignment of electrodes with implants. E. Kajfasz/B. Quinn

  13. Production: Testing • Functionality Test • Debug bad strips (broken capacitors), bonds, chips, etc. • Determine the V-I characteristics of the sensors • Measure V-max p-side breakdown voltage (micro-discharge effect) • Burn-in • Bias the ladder or wedge and test the readout for 72 hours • Measure pedestals, noise, gain and check sparse readout • Laser • Expose biased detectors to a narrow laser scan • Measure the depletion voltage and leakage currents and identify dead channels • Readout tested again after the detector is mounted on a barrel or disk V-max Fail E. Kajfasz/B. Quinn

  14. Production: Vop L6 L3 Vop (V) Vop (V) FW L9 Vop (V) Vop (V) E. Kajfasz/B. Quinn

  15. Production: V-max L6 L9 |V-max| (V) |V-max| (V) FW |V-max| (V) E. Kajfasz/B. Quinn

  16. Production: dead channels L3 % dead strips L6-p L6-n % dead strips % dead strips L9-p L9-n % dead strips % dead strips FW-p FW-n % dead strips % dead strips E. Kajfasz/B. Quinn

  17. Production: Rates Production mainly paced by problems with HDIs and Silicon sensors (yields, delivery delays …) E. Kajfasz/B. Quinn

  18. Production: Detector Quality • Detector classification: • Dead channel: < 40 ADC count response to laser • Noisy channel: > 6 ADC count pedestal width • Grade A: less than 2.6% dead/noisy channels • Grade B: less than 5.2% dead/noisy channels • Only used mechanically OK Grade A and B detectors Channel Fractions (%) E. Kajfasz/B. Quinn

  19. Assembly: Barrel alignment Ladders placed on barrels using an insertion fixture Internal alignment done using a CMM(touch probe) E. Kajfasz/B. Quinn

  20.    Active BH Passive BH Barrel2 alignment - rotations In the plane of the ladder Around ladder short axis Around ladder long axis 10um 48um 48um  (mm)  (mm) (mm) s(d) =48um induces a 3um error s(g) =48um induces a 2um error s(D) =10um induces a 3um error E. Kajfasz/B. Quinn

  21. Assembly: Barrel-Fdisk mating E. Kajfasz/B. Quinn

  22. Assembly: End Fdisks mating E. Kajfasz/B. Quinn

  23. Assembly: Hdisk E. Kajfasz/B. Quinn

  24. Assembly: Radiation monitors E. Kajfasz/B. Quinn

  25. Assembly: ½-cylinder HDI connection to low-mass cable South Half Cylinder E. Kajfasz/B. Quinn

  26. SMT Readout: Data Flow HV / LV I,V,T Monitoring 8’ Low Mass Cable ~19’-30’ High Mass Cable (3M/80 conductor) 25’ High Mass Cable (3M/50 conductor) 3/6/8/9 Chip HDI KSU Interface Board CLKs CLKs Adapter Card SEQ SEQ SEQ Sensor SEQ Controller Optical Link 1Gb/s Detector volume Platform Serial Command Link VRB VRB VRB VBD PwrPC 1 5 5 3 VRB Controller VME VRC L3 Counting House SDAQ E. Kajfasz/B. Quinn

  27. SMT Readout: Electronics • SEQuencers • 6 crates (120 boards) located on the detector platform • Use SVX control lines to actuate acquisition, digitization and readout • Convert SVX data to optical signals • VRBs (VME Readout Buffers) • 12 crates (120 boards) located in counting house • Data buffer pending L2 trigger decision • Input @ 5-10 kHz L1 accept rate ~ 50 Mb/s/channel • Output @ 1 kHz L2 accept rate ~ 50 Mb/s • Interface Boards • 8 crates (144 boards) located inside the detector volume • Regenerates signals • SVX monitoring and power management • Bias voltage distribution E. Kajfasz/B. Quinn

  28. Installation Fiber Tracker • Cylinder installation was completed on 12/20/00 • A ½ cylinder of 3 barrels and 6 F disks was inserted into each end of the CFT bore • H Disk installation was completed on 2/6/01 • The cabling (~15,000 connections) and electronics installation was completed in May 2001 Calorimeter Low Mass Cables SMT High Mass Cables Interface Boards E. Kajfasz/B. Quinn

  29. Commissioning: Status • The entire detector has been connected and powered • The 30% glycol + water coolant is refrigerated at –10 degC (=> detectors run between –5 and 0 degC) • ~15% of the devices are not in the readout: • 10% ladders, 18% F wedges, 20% H wedges • Problems could be with boards, cables, connectors, chips, etc. We will debug each of them during the October/November shutdown, and expect to recover at least half of them. • Currently collecting calibration, alignment and commissioning data E. Kajfasz/B. Quinn

  30. Commissioning; Event Display • Online SMT event display E. Kajfasz/B. Quinn

  31. Commissioning: Monitoring Online event monitoring program E. Kajfasz/B. Quinn

  32. Commissioning: Charge Collection • A cluster is defined as a contiguous sequence of strips with • Each strip  6 ADC counts • Cluster  12 ADC counts • 1 MIP ~ 25 ADC counts • One can play on: • Timing settings, i.e. the delay of the integration window w.r.t. the beam crossing • Preamp bandwith (pabw) E. Kajfasz/B. Quinn

  33. Commissioning: Timing and S/N Higher preamp bandwith does not significantly reduce noise on n-side = 4x132ns + 1x18ns + 0x2ns Highest value  smallest bandwith E. Kajfasz/B. Quinn

  34. Commissioning: Calibrations • SMT pedestal, noise and gain measurements are taken using SDAQ. • Pedestal and noise measurements are used to calculate the threshold per chip to be used in sparse read out E. Kajfasz/B. Quinn

  35. Barrel cluster charge vs eta MC data E. Kajfasz/B. Quinn

  36. 6-chip ladder n-side cluster size fraction vs eta E. Kajfasz/B. Quinn

  37. SMT & CFT Track Matching • Tracks were found separately in the SMT and the Central Fiber Tracker (CFT) • SMT tracks were extrapolated to the CFT at which point the track offsets were measured • Magnet off data r = -3  36 m E. Kajfasz/B. Quinn

  38. SMT-CFT primary tracks E. Kajfasz/B. Quinn

  39. Conclusions • Design/Production • Experience with double-sided detectors has led to the decision to use single-sided silicon for the upgrade. • Should work towards simpler designs in the future. For example, using 6 different sensor types resulted in extensive logistical complications. • Had to overcome numerous vendor related problems for HDIs, Silicon Sensors, jumpers, low mass cables … • Assembly/Installation • First alignment results show that the DØ SMT was assembled and installed very well. • The installation in the D0 detector went rather smoothly. The biggest challenge to overcome was the lack of real estate. The D0 detector, when first designed, was unfortunately not designed with a Silicon detector in mind E. Kajfasz/B. Quinn

  40. Conclusions • Commissioning • The SMT was the first major DØ Upgrade detector system fully operational for Run 2a. More than 85% of the channels were available for readout on startup, and most of the remaining channels will be debugged and recovered by November. • Calibrations and first look at physics show that we understand our detector. • The offline software is debugged at the same time as the hardware. Now that they are both reasonably stable, we can start systematic studies. • The detector should be commissioned by the end of the year. • We are eager to start doing good physics with it. • General • Construction and commissioning of the SMT has been an adventure full of challenges. But thanks to the relentless efforts of many physicists, engineers and technicians, D0 has now a vertex detector to play with. • We had so much fun building this detector for run 2a that we are already planning to build a completely new Silicon Microstrip detector for run 2b (see Alice’s talk) E. Kajfasz/B. Quinn

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