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NES FPGA Emulation System

Ashley Good David Graziano Tim Meyer Ben Petersen Matt Saladin. NES FPGA Emulation System. Advisors Joseph Zambreno Phillip Jones. Project Plan. Design and implement the original Nintendo Entertainment System (NES) in reconfigurable hardware FPGA: Xilinx ML-507

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NES FPGA Emulation System

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  1. Ashley Good David Graziano Tim Meyer Ben Petersen Matt Saladin NES FPGA Emulation System Advisors Joseph Zambreno Phillip Jones

  2. Project Plan • Design and implement the original Nintendo Entertainment System (NES) in reconfigurable hardware • FPGA: Xilinx ML-507 • Xilinx development environment • Develop the individual NES components in VHDL

  3. Central Processing Unit • CPU components are completed and integrated • ALU • IFID • Branch Logic

  4. Central Processing Unit • Testing Plan • Tested • ALU • Instruction fetch/decode • CPU as a whole needs to be integrated and tested with ROM file as input • After CPU is fully tested, it will need to be integrated with the PPU and retested

  5. Picture Processing Unit

  6. Picture Processing Unit

  7. Picture Processing Unit

  8. Picture Processing Unit

  9. Things to be done • Integrate components • Test in Modelsim • Test on FPGA • VGA output • From test program • From NES • Controller interface • Connecting to FPGA board • Accessing controllers from I/O pins on board • Reading a game file store on CompactFlash card

  10. Semester Plan and Schedule 2/25: Have the CPU and PPU completed and tested 3/8: Full NES Modelsim testing 3/15: VGA output from FPGA 3/15: Controller Interface 3/15: Start on board testing 4/15: On board/full system testing 4/15: Poster 4/29: Design Report

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