GOSSIPO-2 chip: a prototype of read-out pixel

1. GOSSIPO-2 chip: a prototype of read-out pixel array featuring high resolution TDC-per-pixel architecture. Vladimir Gromov, Ruud Kluit, Harry van der Graaf. NIKHEF, Amsterdam, The Netherlands. April 18, 2008.

2. Outline • Drift time measurements in the GOSSIP detector. • Time-to-Digital Conversion with local oscillator. • GOSSIPO-2 chip: history, structure and features. • Characterization and performance of the pixel array of the chip. • Conclusions and plans. V.Gromov

3. GOSSIP detector: principles of operation. Gas On Slimmed Silicon Pixel (GOSSIP):a detector combining a thin gas layer as signal generatorwith a CMOS readout pixel array. Cathode (drift) plane Z Cluster1 Cluster2 1mm, 400V Cluster3 Integrated Grid (InGrid) Y 50um, 400V X Slimmed Silicon Readout chip Input pixel 50um • 3-D track reconstruction Cluster’s drift time measurements • low capacitance on the pixel ( down to 10 fF). • narrow drift gap (1 mm). • fast charge collection time (20 ns). • low diffusion of the primary electrons (70 um/1.6 ns) High resolution TDC V.Gromov

4. Time-to-Digital Conversion based on local oscillator. Drift time Pixel_1 Hit signal Local oscillator Clock signal (period is Tslow) Hit Out Start Stop Start Stop Clock Bus Local oscillator: output signal (period is Tfast) Pixel_2 Measured time The number of clocks (Nfast) at the output of the local oscillator gives the value of the drift time as follows: Tdrift = Tslow- Nfast●Tfast Clock signal source • Time resolution is determined by the frequency (Tfast) and performance of the local oscillator circuit. • The local oscillator is active only within restricted space of time. • Only “slow” Clock signal is being distributed across the chip. Low power consumption V.Gromov

5. GOSSIPO-2 chip: history, structure and main features. • History. • 2006. GOSSIPO-1 (0.13um CMOS): analog front-end: • fast, low-noise (ENC=70 e- ) threshold =350 e-, • low-power (2 uWper channel). • 2007. GOSSIPO-2 (0.13um CMOS): • read-out pixel array. • sensitive area: 0.88 mm2 • (16 pixels x 16 pixels) • pixel size: 55 um. • high resolution • TDC-per-pixel architecture (bin=1.8 ns). • -separate TDC block. • -separate local oscillator circuit. • -analog monitor block. V.Gromov

6. Performance of the local oscillator circuit. Schematic of the local oscillator. EN 0ns…Tslow(25 ns) Tfast(1.8 ns) OUT NAND EN OUT Delay = Tfast/2 = Function (Temp, Vdd) 0…15 (4-bit TDC) Effect of the temperature. Effect of the power supply voltage . Tfast,ns Tfast,ns 2% / 10 ◦C - 12% / 100mV Channel-to-channel statistical spread is 4% Power supply voltage, Volts Temperature, ◦C Accumulated error will be kept within 6% (1.8 ns or 1 bin of the 4bit TDC). • If the power supply changes within 50 mV • If the temperature changes within 30◦ C V.Gromov

7. Performance of the TDC block. Hit signal TDC structure. Data Signal at the input of the “slow” clock counter (period is Tslow= 25 ns). Out Local oscillator 4bit“fast” clock Counter Nslow Start Hit Stop Start In Out Output code, converted as Nslow●25 ns + Nfast●1.8 ns Stop Stop Signal at the input of the “fast” clock counter (period is Tfast= 1.8 ns) Out TDC Control Nfast 4bit“slow” clock Counter Clock Trigger signal Trigger In DATA _FORMAT = 4bit (Nslow) + 4bit (Nfast) Read Reset Clock Discontinuity occurs when the Hit signal goes over the leading edge of the slow clock (“slow”) signal. Will be solved. Vdd=1.1 V Vdd=1.2 V Vdd=1.3 V Transition region is about 30 ps! - Time resolution is ( Tfast) is 1.8 ns. - Differential non-linearity is about 0.3● 1.8 ns. - Dynamic range is 4bit (Tslow= 25 ns) is 350 ns. delay of the Hit signal, ns V.Gromov

8. GOSSIPO-2 chip: charge-sensitive preamplifier. Features. Low parasitic capacitance at the input (30fF): - low power consumption (2 µW per channel). - pulse response rise-time is 20 ns - low noise (σn=70 e- ENC) threshold =350 e- Vdd=1.2 V Vb1 Cfb = 1 fF Ib=1 nA time jitter / internal delay ≈ 3 ns Signal size = 2400 e- ∆V Output OPAMP Input Cin Signal size = 800 e- Vb2 Threshold =350 e- 60 0 40 20 80 Time, ns Cpar ≈ 30 fF time jitter / internal delay ≈ 8 ns Time jitter / internal delay = Rise_time ● 5σn / Signal size • In order to confine time jitter to the TDC bin size (1.8 ns) the signal must be larger then 4000 e-. • The DC feedback circuit is not tolerant for variation of the fabrication process. This results in a number of not operational channels (15 %-30 %). This will be solved in the future. V.Gromov

9. GOSSIPO-2 chip: voltage comparator. Vdd=1.2 V • Features. • The comparator is an OPAMP based on current mirrors architecture. • the internal delay is inverse proportional to the size of the input signal (as usual). • the minimum value of the internal delay (∆tmin) is much larger than one bin of theTDC (1.8 ns). • ∆tmindepends on the value of the tail current (Itail) and therefore • ∆tminis temperature dependent • ∆tminis power supply voltage dependent • ∆tmintakes different values due to channel-to-channel mismatch. Itail Output Input Vthr I tail = 0.2 uA Comparator delay Threshold =350 e- Itail= 0.4 uA I tail = 0.8 uA ∆tmin=15 ns ∆tmin=10 ns ∆tmin=7 ns 1000 2000 Signal size, electrons 3000 4000 • Currently we are developing a faster comparator having internal delay close to 1.8 ns (one bin of the TDC) even at low tail currents (0.4 µA). Instability and spread of the value of ∆tmin will be negligible. V.Gromov

10. GOSSIPO-2 chip: read-out pixel array. Pixel_2 Pixel_16 Pixel_1 Common threshold Data Pixel_256 4bit Threshold DAC • Functionality. • Only “Slow” clock (40 MHz) is being distributed across the array. • All 256 pixel will be read out serially when the Read (Trigger) signal arrives. • “Clear_ON” mode: data on the pixel will be RESET locally if the Read signal is not available within 350ns after the hit signal. • “Clear_OFF” mode: data on the pixel will be KEPT UNCHANGED even if the Read signal is not available within 350ns after the hit signal. • 4 bit DAC for threshold tuning. • - Control registers for masking and test-pulse enabling. Input pad Data Local threshold Out TDC block In Comp Preamp Reset Clock Front-end Read (Trigger) Test pulse V.Gromov

11. Test set-up for the GOSSIPO-2 read-out pixel array. Clock (“slow”) generator 40MHz. DC source Clock power supply voltage Common threshold Pulse generator test pulse GPIB GOSSIPO-2 Read (trigger) FPGA USB V.Gromov PCB with GOSSIPO-2 PCB with FPGA & USB port PC with LabView FPGA & software: Upload configuration data (threshold DACs and mask registers). Readout chip data. Read(trigger) signal and test pulse.

12. Time resolution as a function of threshold value. Threshold scan. Pixel cell structure. 500 time jitter ≈ 4bin●1.8 ns = 7.2 ns Data Signal size = 1200 e- Threshold voltage, mV Out 400 TDC block In Front-end 300 noise 600 Threshold voltage, mV time jitter ≈ 2bin●1.8 ns = 3.6 ns Signal size = 3000 e- Reset Clock 500 Read (Trigger) Test pulse Threshold 400 300 time jitter ≈ 1bin●1.8 ns = 1.8 ns 700 Signal size = 12000 e- ∆V(Qin) Threshold voltage, mV Test pulse 600 Measured time 500 Read (Trigger) signal 400 300 160 110 150 130 120 100 80 140 90 70 Measured time (converted output code), ns - Low threshold operation (350 e-) in combination with large signal size (larger than 4000 e-) will allow for high time resolution (jitter less than 1bin of the TDC = 1.8 ns). V.Gromov

13. Time scan. Pixel cell structure. Measured time (converted output code ) as a function of the delay of the Test pulse. Large signal (> 4000 e- ) and low threshold operation (350 e-). Data Out TDC block In Front-end Distortion occurs when the Hit signal goes over the leading edge of the slow clock (“slow”) signal. Reset Clock Read (Trigger) Test pulse Threshold (350e- ) Measured time (converted output code) [ns] transition region ≈ 1 ns Test pulse ∆V(Qin >4000e-) delay Measured time Read (Trigger) signal Delay of the Test pulse, ns - The complete read-out chain demonstrates good time resolution (transition region is 1ns) when the threshold is low (350e-) and the input signal is large (>4000e-). V.Gromov

14. Threshold equalization in the pixel array. Generation of the pixel’s threshold voltage. Common threshold voltage Local threshold voltage 4bit Threshold DAC Serial Link Serial Link Configuration memory Preamp output Before equalization. Threshold offset, mV 600 Offset Pixel_1 500 160mV 400 Common threshold Offset Pixel_2 Offset Pixel_3 300 Not operational pixels (15%). 200 After equalization. Preamp output Threshold offset, mV 500 These pixels should be masked Common threshold 400 300 Precision = 160 mV/16(4bit DAC) = 10 mV (150e-) 200 0 50 100 200 250 150 Pixel number - Threshold spread after equalization per pixel: 150 e-. V.Gromov

15. Channel-to-channel spread of the measured time. Distribution of the value of the measured time (converted output code ). Threshold equalization has been done. Large signal (> 4000 e- ) and low threshold operation (350 e-). Pixel array. Output Code_1 time interval ≈ 4bin●1.8 ns = 7.2 ns Pixel_1 120 Entries Output Code_2 Test pulse Pixel_2 90 60 Output Code_256 Pixel_256 30 Read Reset Clock 0 115 118 121 124 127 130 Measured time (converted output code), ns • Due to uneven delay inside the read-out circuit the pixels will give different values for the measured time (converted output code). These values are spread across 4 bins of the TDC (7.2ns). • - In the future we will solve this problem by means of using a faster comparator (internal delay close to 1.8 ns). V.Gromov

16. Conclusions and plans. • A small chip sensor array has successfully been prototyped in the GOSSIP0-2 chip in 0.13 μm CMOS technology. • The TDC per pixel with local oscillator satisfies the design requirements: low power consumption, high time resolution (1.8 ns bin) and simplicity. • The front-end circuit of the pixel’s readout will benefit from the low detector parasitic capacitance and no need to compensate for the leakage current. • Low threshold (350 e-) and fast peaking time (20 ns) enable for high quality drift time measurements (jitters 1.8 ns) at large input signals (>4000 e-) and after accurate threshold equalization. • Plans: • The DC feedback in the preamplifier will be revised (matching). • A faster comparator circuit is required in order to reduce internal delay, spread and jitter. • A small-area detector will be constructed on top of the GOSSIPO-2 chip. This detector will be tested on the beam in the end of 2008. V.Gromov

17. Additional slide. Protection against discharges. Layout of the input pad 20um Polymide High Resistive Amorphous Silicon 3um Oxide Metal layer TD Metal layer LM Rprot ≈ 1MΩ Qdischarge Rfb Output A Cp-sub≈ 10fF Cp-grid≈ 0.5fF - protective resistor causes neither signal distortion nor noise increase as long as Rprot●Cp-grid is less than 1ns. V.Gromov

18. Additional slide. Integrated Grids. V.Gromov

19. Additional slide. Time scan. Threshold equalization has been done. Low threshold operation (350 e-). Measured time (converted output code) [ns] Measured time (converted output code) [ns] Signal = 3000 e- Signal = 1200 e- Delay of the Test pulse, ns V.Gromov