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Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration D

This article discusses the basics of reconfigurable technology, focusing on fine-grain reconfiguration. It explores the challenges and goals of creating reconfigurable systems, as well as the methodology for high-level analysis and system definition. The article also covers micro-reconfiguration and verification techniques.

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Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration D

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  1. Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration D. Pnevmatikatos, T. Becker, A. Brokalakis, K. Bruneel, G. Gaydadjiev, W. Luk,K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, M. Robart, M. D. Santambrogio, D. Sciuto, D. Stroobandt, and T. Todman CatalinCiobanu Chalmers University of Technology

  2. Reconfigurable Technology Basics Technology for practical adaptable hardware systems • Can add/remove components at run-time/product lifetime • Flexibility at hardware speed (not quite ASIC) • Parallelism at hardware level (depending on application) • Ideally: alter function & interconnection of blocks Implementation in: • FPGAs: fine grain, complex gate + memory + DSP blocks • Coarse Grain (custom) chips: multiple ALUs, multiple (simple) programmable processing blocks, etc.

  3. FASTER Motivation Focus on fine-grain reconfiguration (but not-limited) Creating reconfigurable systems is not straightforward! • The designer has to: • Identify portions to be reconfigured • Establish a schedule that (a) respects dependencies (b) achieves performance and other constraints • Manage the system resources (reconfiguration area mainly) • Reconfiguration cost is substantial (use wisely) • Verify a changing system! • Tool support for these tasks is esoteric to say the least • Resource management is up to the user • Verification: any support today?

  4. FASTER Goals & Innovation • Include reconfigurabilityas an explicit design conceptin computing systems design, along with methods and toolsthat support run-time reconfiguration in the entire design methodology • Provide a framework for analysis, synthesis and verification of a reconfigurable system • Provide efficient and transparent runtime support for partial and dynamic reconfiguration, including micro-reconfiguration • Demonstrate usability & performance with commercial applications (Maxeler, ST Microelectronics, Synelixis)

  5. FASTER Overall Methodology

  6. High-level Analysis & Reconfigurable System Definition (led by PoliMi) Analyse each application to: • Define the application components • Static part, reconfigurable modules, software part • Provide analytical model of a reconfigurable design • Relate application attributes with implementation parameters • Estimate metrics (speed, area, power) • Identify and optimize performance and constraints on the target reconfigurable system • Execution time • Floorplanning/Placement • Reconfiguration time

  7. High-level Analysis & Reconfigurable System Definition – cont’d Achieve these by identifying: • partitioning of the input specification in HW/SW components • implementation(s) of the modules to be realized as HW accelerators • the most appropriate level of reconfigurability for HW components: none, micro, region based • foorplanning constraints (size and shape) • placement requirements • power constraints • a baseline schedule for application’s execution

  8. High-level Analysis & Reconfigurable System Definition – Proposed Flow • Platform • Architecture • App Task Graph • Performance • Characteristics High-level analysis Estimation of metrics (power, speed, area) App task profiling + Identification of reconfigurable cores Optimization of app for micro-reconfiguration Off-line scheduling and mapping into reconfigurable regions

  9. Micro-reconfiguration (led by Gent) In some applications we can identify fast changing inputs vs. slow‐changing  “parameters” • Parameters trigger a small-scale reconfiguration We want to: • Identify parameters • Create bitfile with “holes” • Parameter values => reconfiguration bits for missing “holes” • Fine grain, faster reconfiguration time! • Extend the idea from logic (TLUT) to wires (TCON)

  10. Micro-reconfiguration (led by Gent)

  11. Micro-reconfiguration (led by Gent)

  12. Verification: (led by Imperial) • Traditional approach to verification: extensive simulation • Have we covered all the cases? • Our approach: • Combine symbolic simulationwith equivalence checking • General and modular • Demonstrate for Maxeler kernels • Novel compiler from Maxeler to symbolic simulator • Use Yices as equivalence checker • Use run‐time verification when static approaches cannot verify the entire RC system. Minimize impact on: • Speed, area and power • Use light‐weight architectural support

  13. Verification: Compare source & target Target Design optimization Source Transformations Compile to simulation Compiler Source Target Symbolic input Symbolic simulator Symbolic simulation Output (from source) Output (from target) Target Source Checker Validation Yes No Equivalent? Not equivalent, couter-example Equivalent

  14. Run-time System (Chalmers/FORTH) • Provide support for partial & dynamic reconfiguration • Extend the OS capabilities, integrate in existing systems • Efficient on-line scheduling and placement of task modules • Evaluate reconfiguration overhead • Propose advanced mechanisms to support • Scheduling • Relocation • Fragmentation = f(relocation, scheduling) • Area allocation • Bottom-line: Extent the flexibility of run-time support

  15. FASTER Run-time System Area allocation Scheduling Improve: -Speed -Power -Temperature Placement Fragmentation Routing Relocation Prefetching

  16. Demonstration and Use • Use three complex applications from different application domains and on commercial platforms: • (a) Reverse Time Migration (RTM), a computational seismography algorithm (Maxeler, high-performance) • (b) Global Illumination and Image Analysis (ST, desktop) • (c) a Network Intrusion Detection System (Synelixis, embedded) • Evaluate the FASTER tool flow on designer productivity in the design and verification process. • Metrics: application speed, cost, and power consumption.

  17. Expected Results & Conclusions FASTER is a focused project that builds on combined partner expertise as well as on past research work & projects We focus on (and hope to demonstrate): • productivity improvement in implementation and verification of dynamically changing systems • total ownership cost reduction (NIDS and RTM systems) • performance improvement under power constraints for Global Illumination and Image Analysis application

  18. Challenges & Opportunities Tool support for analysis & system definition Specification of changing system(s) Reconfigurable granularity: influenced by (influences???) tools and applications Architectural support for reconfiguration (vendor?) Metrics: include design effort/time, total ownership cost

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