Presentation to MAPLD 2001 11-13 September 2001

1. MEMS-based Reconfigurable Manifold Warren Wilson1, Jim Lyke1, and Paul Contino21Air Force Research Laboratory, Kirtland AFB, NM 87117-57762Elizabethtown College, Elizabethtown, PA Presentation to MAPLD 2001 11-13 September 2001

2. Outline • Motivation • Adaptive Manifold Concept • Relays for the Adaptive Manifold • Design of Simple Test Manifold • Conclusions

3. Outline • Motivation • Adaptive Manifold Concept • Relays for the Adaptive Manifold • Design of Simple Test Manifold • Conclusions

4. Motivation for Reconfigurable Systems • Maximizes utilization of space assets to allow: • Recovering from faults (fault-tolerance) • Reconfiguration after deployment • Reconstituting / “refocusing” assets for current mission • Reconfiguring / “refocusing” assets for new missions • Single platform and distributed functionality • Accelerates the possibility of “space-on-demand” by enabling plug-and-play spacecraft • Adaptive interfaces to dramatically reduce the time for development, integration • Space logistics / remote servicing

5. Levels of Reconfigurability • Reconfigurable computing • von Neumann architecture • reconfigurable processing • Reconfigurable electronics • agility in analog • agility in power • Reconfigurable systems • adaptive wiring manifolds instructions gates,interconnect electrical signals electronic pathways “real world”

6. Reconfigurable computing • “Von Neumann” computers – configure registers to enable stored-program computation • FPGA-based computers – configure entire digital description to permit ad hoc computation concepts • Techniques limited to digital systems • Can’t reconfigure sensor amplifiers • Can’t alter antenna structures • Can’t alter radio-frequency equipment circuitry

7. Reconfigurable analog • Programmable analog architectures • Configurable process chains • Alter gain, offset, filtration characteristics • Configurable analog blocks • Permits flexible arrangement of some analog building blocks • Limitations • Frequency of operation • Ranges of resistances, capacitances require supplemental, external, non-programmable discrete components

8. Reconfigurable Power • permit alteration of input voltage, output voltage, and load conditions under software control • maintain optimal electrical efficiency under variations • Industry practice • Some configurable power technologies permit modular power supplies by manual arrangement of discrete building blocks • Smart-power approaches in microprocessors and FPGAs to permit different supply and I/O voltage levels

9. Reconfigurable Microwave • Emergent techniques • Direct digital synthesis (generated modulated carrier directly in real-time) • Reconfigurable antenna • Electronically steerable antenna • MEMS-based antenna reshaping • Other techniques to modify dielectric / conductor configurations of antenna under software control • Software radio • Minimize non-digital content of rf systems, permit agile manipulation of radio protocols for transceivers

10. Reconfigurable digital Reconfigurable analog Reconfigurable microwave Reconfigurable power A/D D/A Role of Adaptive Wiring in Future Reconfigurable Systems Adaptive Manifold of Reconfigurable Interconnections component sockets connectors A/D D/A discrete component patchboard

11. Outline • Motivation • Adaptive Manifold Concept • Relays for the Adaptive Manifold • Design of Simple Test Manifold • Conclusions

12. Adaptive Manifolds • Approaches to embed large numbers of micro-relays into packages, boards, and wiring harness • Strategies for reconfiguration • Algorithms for altering system configurations • Satellite itself becomes a large “field programmable device” • Concepts for repair-ability and extensibility • Disciplines for design and application of reconfigurable systems Smart-wiring based avionics system Dockable-assemblies Satellite-as-a-device

13. A M B N C O D P E Q F R G S H T I U J V K W L X switchbox switch

14. A M B N C O D P E Q F R G S H T I U J V W X

15. A M B N C O D P E Q F R G S H T I U J V K W L X

16. Adaptive Manifold Concept • Use of concepts from field programmable gate arrays (FPGAs) and field programmable interconnect devices (FPIDs) • FPIDs  switch boxes (one or more switches) • FPGAs  collection of switch boxes and wiring patterns to external terminals

17. Representation of wires and switches as a graph A A B C D B E F F E D C

18. Outline • Motivation • Adaptive Manifold Concept • Relays for the Adaptive Manifold • Design of Simple Test Manifold • Conclusions

19. Summary of switch requirements for an adaptive manifold • Bistable / multistable • Electrical performance • Low resistance • Bandwidth • High-isolation (low crosstalk) • Hot-switching

20. Latching Relay Requirements

21. Previous MEMS Relays • Most MEMS switches are momentary contact • Inadequate for configuration purposes • Early work sponsored by AFRL • Thermally actuated switches • LIGA-based • Problems with undercutting prevented electrical actuation from working correctly Typical electrostatic switch - momentary contact Thermally actuated switch - bistable

22. Microlab’s DC Latching Relay Moving contact pad Moving contact (teeter-totter) Fixed contact pad Torsion suspensions Coil contracts

23. Important Microlab Relay Parameters • 50 micron gap • Sets maximum switching voltage • 2 micron thick gold contacts • Sets lifetime under hot switching • 0.2 m/s contact velocity • Related to lifetime under hot switching • 70 mΩ constriction resistance • Sets maximum cold current • 50/200 μs lag open/close time • Sets maximum relay duty cycle

24. Microlab’s DC Latching Relay

25. MEMS HDI Cavity Cavity Metal via MEMS structure Adhesive Kapton Substrate

26. 100 micron deep Via This depth of via was, in itself, quite an accomplishment by GE

27. Pad Geometry for Latching Relay Coil Contact Pad Coil Contact Pad Pivot points Outline of cavity Signal Line Contact Pad Signal Line Contact Pad

28. RF test structure Vias to coil pads Coplanar wave guide probe pads Vias to relay pads

29. Packaging Effort Problems • First-pass results relatively low yield • Tent-pole formation due to post defects • Contaminants and voiding problems • Cavity alignment and die-edges • Experience useful in second-pass work • Improved die preparation / handling • Improved deep via process Tent-pole resulting in un-desired separation Adhesive flow Into MEMS cavity Via voiding

30. FY02 Plans for Micro-Lab Relay • Continue exploration of HDI packaging approach • Development of chip-scale package prototype • Some consideration of co-fired ceramic back-up approaches • Pursuit of improved and denser relay configurations • Establish and improve microwave, power electronic performance ceilings • Reliability work • Continue low-level Au-Au surface contact investigations (VSSE collaboration with Sandia National Laboratory) • Investigate methods of improving arcing performance for hot-switching Multi-chip package (co-integrated control Components) Atomic Force Microscopy results for representative surface (courtesy of VSSE/Capt Tringe)

31. Outline • Motivation • Adaptive Manifold Concept • Relays for the Adaptive Manifold • Design of Simple Test Manifold • Conclusions

32. Design of Simple Test Manifold • Construct a macro-relay version of a simple manifold • 64 conventional relays in a “tree of mesh” configuration • Circuit board on printed wiring board • Expected benefits • Development of control circuitry • Establish software algorithms and user-interface • Examine scaling issues

33. Tree-of-meshes for test board design 41 N19 42 43 N22 44 N23 N20 N21 N9 33 34 35 36 N18 25 26 27 28 N9 N18 17 18 19 20 N5 N14 N17 N6 N7 N8 N15 N16 1 2 3 4 5 6 7 8 N1 N2 N3 N4 N10 N11 N12 N13

34. t in c’ c Test Board Approach input (in) Transfer (t) on off Bipolar drive Circuits (2 per relay) (5V) c c’ SPST relay

35. D Q Q D Q D Q D D Q D Q D Q Q D D Q D Q S R Q t t t in in in c’ c’ c’ c c c Example control circuitry clock out clock data out data reset to all Sequential components done in sentinal chain one shot S R Q transfer chain one shot done 100hz osc. ckt0 ckt1 ckt63 relays

36. Routing Algorithms and User Interface • Standard algorithms from FPGA routing • Djikstra’s shortest-path • Heuristics for graph Steiner tree/forest (not implemented) • Generates bitstreams for manifold to program from PC • User interface implemented in TCL

37. Forecast • FY02 • Refine micro-relays and packaging • Development and test of single and multiple board versions of adaptive manifold to demonstrate scalability • Availability of prototype packaged configurations • FY03 • Development of integrated controller ASIC • Development of single and array forms of micro-relays for manifold applications with integrated control • Availability for space qualification and test development planning

38. Summary • Adaptive manifold described based on FPGA / FPID concepts and micro-latching relays • Establishes a basis for totally reconfigurable systems when combined with other methods • Basic architecture concept introduced • MEMS-based relay technology development program discussed • Simple test manifold breadboard system discussed