The changing Supply Chain How to address R&D challenges

1. Luc Van den hove  imec 2008

2. The changing Supply ChainHow to address R&D challenges Luc Van den hove Executive Vice President Chief Operating Officer IMEC

3. Outline • From 45nm to 22nm:A few process technology challenges and trends • Lithography Options • CMOS Transistor Scaling • 3D integration • Cost effective R&D partnership, bringing together the various players of the supply chain Luc Van den hove  imec 2008

4. Lithography based scaling: 2D scaling Feature size (½ pitch) reduction continues 200 DRAM Logic 100 80 NAND Flash 60 Resolution, "Shrink" [nm] 50 40 30 20 Jan-02 Jan-03 Jan-04 Jan-05 Jan-06 Jan-07 Jan-08 Jan-09 Jan-10 Jan-11 Jan-12 Jan-13 Jan-14 Year of Production Start Source ASML Luc Van den hove  imec 2008

5. EUV lithography Functional 32nm SRAM cells (0.186 mm2) 40 nm lines/spaces Contact layer 35 nm lines/spaces First 40/35nm L/S using Sn source @ imec Luc Van den hove  imec 2008

6. CMOS scaling graphene nanowires Ge/IIIV 25 nm 25 nm NiSi NiSi FinFET ArF + RET metal gate HfO 2 ArF immersion high -k FUSI strain Double Patterning USJ silicide EUVL Cost / function Device Performance time

7. CMOS scaling 32-22nm: FinFET Device graphene Cost / function NiSi 45-32nm: High-k / metal gate integration poly-Si SOI FF Fin Gate first Gate last ArF + RET ArF immersion 50 nm Bulk FF Double Patterning Source: INTEL, ChipWorks 10 Lg=32nm EUVL nanowires Ge/IIIV FinFET 16 and beyond metal gate High-m materials, New devices HfO 2 32 - 22 - 16 high -k 25 nm 25 nm NiSi Non-planar devices NiSi FUSI Device Performance 45 - 32 strain High - k, Metal Gate USJ 90 - 65 - 45 silicide time >=130 Strain, USJ Luc Van den hove  imec 2008

8. CMOS Scaling New materials and devices will be needed to continue the performance scaling graphene Cost / function ArF + RET ArF immersion Double Patterning EUVL nanowires Ge/IIIV FinFET 16 and beyond metal gate High-m materials, New devices HfO 2 32 - 22 - 16 high -k 25 nm 25 nm NiSi Non-planar devices NiSi FUSI Performance 45 - 32 strain High - k, Metal Gate USJ 90 - 65 - 45 silicide time >=130 Strain, USJ Luc Van den hove  imec 2008

9. CMOS scaling CNT 3D TSV Air gap graphene 3D SIP 3D SIP Low kk=2.5 Low k k=2.7 Interconnects Low k k=3.0 Cu nanowires Ge/IIIV FinFET metal gate HfO 2 high -k 25 nm 25 nm NiSi NiSi FUSI strain FEOL Device roadmap USJ silicide time Luc Van den hove  imec 2008

10. 3D Integration R&D Roadmap N-layer UTCS 3D-SIC A D V A N C E D P A C K A G I N G A N D I N T E R C O N N E C T 3D-SIC N-layer 3D-SIC 2-layer 3D-SIC N-layer UTCS 3D-WLP N-layer UTCS Chip-in-Flex UTCF Ultra-Thin-Chip Embedding 2-layer UTCS 3D-WLP N-layer 3D-WLP 3D-WLP 2-layer Through-Si Face-to-Face Micro-bumps 3DSIP Die-in-board Face-to-Face Flip-Chip 3D-SIP CSP 3D-SIP BGA Stacked-IC Package 3D-SIP 2005 2007 2008 2009 2004 2006 2010 3D Interconnect Complexity Research Roadmap Luc Van den hove  imec 2008

11. Huge R&D challenge Need for R&D has never been as high Cost of R&D is rapidly increasing CAGR semiconductor industry: 5-7% R&D cost increase per year: 20-30% Relentless reduction of feature size “2D scaling” Explosion of New Materials in Advanced Devices Outsourcingof R&D to shared R&D platforms Increased use of 3rd dimension “3D scaling” Luc Van den hove  imec 2008

12. The world is rapidly changing(e.g. the Logic IDM landscape) Foundries require technology leadership Technology leadership requires huge research effort(and traditional sources of research are drying out) Cost-effective research modelwill become even more important Because of the increasing R&D cost, many classical IDMs rapidly migrate to Fablite model Luc Van den hove imec 2008

13. The world is rapidly changing(e.g. the Logic IDM landscape) IDM’s Fablite Fabless EquipmentMaterialsSuppliers Shared R&D platforms Foundries Changing R&D supply chain Luc Van den hove imec 2008

14. Partnering for Cost-effective Research Memory IDM Logic IDM EquipmentSuppliers Foundries Material Suppliers Fablite Fabless SAT Assemby & Test EDA suppliers Build critical mass Share R&D cost World-wide Centralized Research Platform Luc Van den hove imec 2008

15. STMicroelectronics Shared R&D Platform Participation from most major players from the supply chain Luc Van den hove imec 2008

16. Global R&D platforms Shared R&D Platforms Universities Providing focus for universities and basic insight and solutions for industrial partners Longer term, many options Industry Time frame Shorter term, applications Lower Higher R&D cost Luc Van den hove imec 2008

17. Luc Van den hove  imec 2008