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NASA Testing Anomaly Update

Briefing: Independent NASA Test of RTSX-SU FPGAs. NASA Testing Anomaly Update. Presented by Dan Elftmann- Actel Investigators: Don Kinell- Actel Marco Cheung- Actel Bashar Aziz- Actel Wednesday February 16 th 2005. Anomaly Preview.

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NASA Testing Anomaly Update

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  1. Briefing: Independent NASA Test of RTSX-SU FPGAs NASA TestingAnomaly Update Presented by Dan Elftmann- Actel Investigators: Don Kinell- Actel Marco Cheung- Actel Bashar Aziz- Actel Wednesday February 16th 2005

  2. Anomaly Preview

  3. KU1- S/N 50955 Cannot duplicate failure Prior to Burn In Reason for investigation: High temperature functional fault History after Programming • Passed room temperature testing on ATE • Passed cold temperature testing on ATE • Failed hot temperature testing on ATE • Re-tested at room temperature on ATE - Failed • Passed repeated bench level test attempts • Returned to ATE and passed room, cold, and hot tests • Uploaded for 250 hours Burn In with KU1 second upload • Passed room temperature ATE after 250 hours • Passed ATE after LTOL (-55C) shutdown at 115 Hours • ATE debug log examination found no pattern of failure Current Actions • None - Placed back into KU-1 lot for continued LTOL testing Next Steps • Final Report – 3rd week in February

  4. KU1- S/N 50718 Confirmed ESDPrior to Burn In Reason for investigation: Out-of-Family ICCA current History after Programming • Passed room temperature testing on ATE • ATE measured ICCA current value was 1.72mA • Flagged for further investigation as Out of Family– NOT out of specification • IEEE 1149.1 JTAG testing found that the device ID code could not be read • Bench testing revealed ICCA dependency to voltage levels on TCK input pin • TCK pin at logic level “1” => ICCA = 60uA • TCK pin at logic level “0” => ICCA = 1.8mA • 1st Suspect: sensitive ESD device, transistor N3b in TCK pad circuit • TCK schematic examination revealed TCK signal path does not utilize N3b • 2nd Suspect: 2-input NOR gate (NMOS transistor N2– schematic next slide) • Transistor N2 is in the direct signal path of TCK • FIB (Focused Ion Beam) pads added at multiple TCK signal path nodes • Micro probing confirmed: • TCK output signal to the IEEE 1149.1 circuitry stuck near high voltage level • 2-Input NOR Gate in TCK input circuit not functioning • De-processing to bare silicon revealed ESD in TWO NMOS transistors • Primary site– N2 Transistor of 2-Input NOR Gate (schematic next slide) • Secondary site– N3b transistor in user input signal path circuitry from TCK pin

  5. KU1- S/N 50718 Confirmed ESDTCK I/O Schematic with FIB pad locations

  6. KU1- S/N 50718 Confirmed ESDESD Damage at Primary site Photo shown: • high resolution SEM on Failed unit from a 45° tilt at transistor N2 location • N2 is within the 2-input NOR gate circuit in the signal flow path for TCK clock • Photo is post HF strip to the silicon level • Revealed signatures of damage that were obscured by overlaying layers

  7. KU1- S/N 50718 Confirmed ESDESD damage at Secondary site(1 of 2) Photo shown: • Failed unit high resolution SEM of transistor N3b • N3b is an NMOS pull down within the first stage inverter of the user I/O input path • For NASA design this path is not functionally used • Photo is pre-Oxide etch ESD Pin Hole Evidence GNDQ (SOURCE) INX (DRAIN) Transistor N3b

  8. KU1- S/N 50718 Confirmed ESDESD Damage at Secondary site(2 of 2) Photo shown: • Failed unit high resolution SEM from a 45° tilt of Transistor N3b • N3b is not functionally utilized for the signal flow path of TCK • Photo is post HF strip to the silicon level • More damage observed beyond pin hole observed with gate oxide in place TRANSISTOR N3b GNDQ (SOURCE) INX (DRAIN) EXTENSIVE ESD EVIDENCE

  9. KU1- S/N 50718 Confirmed ESDPrior to Burn In Current Actions • Failure Analysis complete • Second Draft of Final Report in Review Next Steps • Final Draft 3rd Week in February

  10. KU1- S/N 50956 Delay Path IncreaseAfter 500 hours HTOL & 115 hours LTOL Reason for investigation: Delay measurement increase after 115 hours LTOL History after Programming • Passed all testing after 250 hours of HTOL • Passed all testing after accumulative 500 Hours of HTOL • After 115 Hour LTOL • ATE delay measurement Increased by 10.2 ns with respect to time 0 delay measurement • Mean delay delta for the entire KU1 lot was +3.75 ns • 330th Delay stage verified to have net responsible for 6.4 ns of delay with Silicon Explorer • Silicon Explorer tri-temperature testing • 25ºC testing verified results from ASE (Automatic Silicon Explorer– custom internal Actel tool) • 25ºC manual Silicon Explorer testing confirmed increased delay • -55ºC Silicon Explorer testing verified increased delay • 125ºC testing showed normal delay • 25ºC testing also showed normal delay • Repeat of –55ºC Silicon Explorer testing showed normal delay • Unit sent to NASA for real time monitoring at -55ºC • Tested at –55 ºC with real time monitoring for 6 days on a Burn In Board (BIB) • Real time monitoring method detailed on next slide

  11. KU1- S/N 50956 Delay Path IncreaseMeasurement Technique

  12. KU1- S/N 50956 Delay Path IncreaseNormal Timing Diagram • How do you automate this measurement? • Remember TPD will vary over temperature • Approximately .25% per degree Celsius

  13. KU1- S/N 50956 Delay Path IncreaseMeasurement Technique • Scope measures Delay_out  HCLK • This is like remainder or modulus arithmetic • As 8MHz(HCLK)  Delay_out reference edge moves to the left (faster) with reduced temperature the scope measured Delay_out value increases • If Delay_out value edge moves far enough to the left then the reference edge will change over to N-1 and measurement value will show a dramatic decrease • If the delay  is linear with T, this will result in a saw tooth pattern • A delay shift of exactly one period could go undetected, but is unlikely

  14. KU1- S/N 50956 Delay Path Increase Single Scope Capture FOUT 8 MHz

  15. KU1- S/N 50956 Delay Path Increase Reference + HL + LH measurements

  16. KU1- S/N 50956 Delay Path Increase Temperature Chambers

  17. KU1- S/N 50956 Delay Path IncreaseAfter 500 hours HTOL & 115 hours LTOL History after Programming (con’t) • After 6 days at –55ºC unit was returned to Actel for ATE testing • Unit passed tri-temp testing and showed no indication of the anomalous delay • Unit sent to NASA for real time monitoring during Dynamic operation in a Thermal Cycling environment • Thermal cycled on BIB with real time monitoring of Delay Line • 3 hours at –55ºC • Transition at 1ºC per minute to 85ºC • 3 hours at 85ºC • Transition at 1ºC per minute to -55ºC • Repeat sequence • Thru 31 total days of thermal cycling there have been no observed increases in the Delay Line • One anomaly observed scope, probes suspected Next Steps • Thermal Cycling test to be shut down at NASA GSFC and unit returned to Actel • Unit will be tri-temperature tested on ATE at Actel • Cross Section of all vias and antifuse in observed anomalous net

  18. KU1- S/N 50956 Delay Path IncreaseAfter 500 hours HTOL & 115 hours LTOL

  19. KU2- S/N 50952 Confirmed ESD damagePrior to Burn In Reason for investigation: “Set_n” pin signal stuck high History after Programming • Passed Room Temp R/R on ATE • Failed Cold Temp R/R on ATE • Failed Room Temp R/R on ATE • Silicon Explorer Testing revealed output of “Set_n” buffered signal is stuck high • Curve trace of pin 53– Showed expected I/V curve • I/O Circuit schematic examination revealed Transistor N3b as likely suspect • FIB (Focused Ion Beam) pads added at multiple “Set_n” signal path nodes • Micro probing confirmed: • “Set_n” output stuck near high • De-processing to bare silicon revealed ESD in NMOS Transistor N3b Current Actions • Writing Final Report Next Steps • First Draft – 2nd Week in February

  20. KU2- S/N 50952 Confirmed ESD damageSet_n Schematic with FIB pad locations

  21. KU2- S/N 50952 Confirmed ESD damage ESD damage in user input circuitry ESD EVIDENCE TRANSISTOR N3b Damage observed in Transistor N3b from source to drain INX (DRAIN) GNDQ (SOURCE)

  22. KU2- S/N 50952 Confirmed ESD damage I/Os close to GNDQ higher risk for ESD TCK PIN FAILURE IN UPPER LEFT CORNER RTSX32SU DESIGN LAYOUT NEARBY GNDQ PINS SET_N FAILURE IN LOWER LEFT CORNER

  23. KU2- S/N 54948 Out of Family ICCAPrior to Burn In Reason for investigation: Out of Family ICCA current History after Programming • Room temperature passed read & record on ATE • -55ºC passed functional with Out of Family ICCA current (~1.5mA) • ICCA current persistent at all temperatures • Bench level testing using the IEEE 1149.1 JTAG verified correct checksum • Unit not needed to meet 150 unit quantity for KU2 lot upload Current Actions • Failure analysis on hold pending investigator availability

  24. KU2- S/N 50906 LED False Failure Post 250 hour Burn In anomaly Reason for investigation: BIB LED off at download History after Programming • 250 Hour HTOL • Burn In Board (BIB) LED off at end of test (download) indicating a potential fault • Unit passed all ATE and bench testing, including all deltas • Socket of BIB determined to be damaged • Reloaded with KU2 lot for 500, 750, and 1000 hour uploads • Unit passed at ATE after 500, 750, and 1000 hour Burn In periods • BIB removed from experiment

  25. KU2- S/N 50968 Cannot duplicate Failure Post 500 hour Burn In anomaly Reason for investigation: Functional Fault on I/O Shift Register History after Programming • 500 Hour HTOL • Room temperature functional failure on I/O Shift Register (IO_Monitor output pin) • Repeated ATE test multiple times, unit passed all attempted re-tests • Unit passed verification on bench test • Reloaded with KU2 lot for 750 hours upload • Unit passed ATE test after 750 hour Burn In • Loaded with KU2 lot for 1000 hour upload • Unit passed ATE test after 1000 hour Burn In Current Actions • Unit with remainder of KU2 lot waiting for LTOL testing

  26. KU2- S/N 54954 VIH level shiftAfter 1000 hours HTOL Reason for investigation: “Set_n” pin VIH Level Shift History after Programming • 1000 hour HTOL • VIH level (3.65V) shifted by more than 300mV from time 0 measurement • Single input pin pin 53 (“Set_n”) exceed CMOS I/O standard specification limit of 3.5V • Bench level testing using the IEEE 1149.1 Boundary Scan Register method correlated to ATE measured VIH for pin 53 (“Set_n”) • Curve trace of pin 53– Showed expected I/V curve • Suspect – Partial ESD damage to transistor N3b in I/O buffer Current Actions • I/V Curve Trace of VCCI with respect to GNDQ of S/N 54954 Unit & Reference Unit Next Steps • FIB pad addition underway for signal INX micro probing • Micro probe FIB Pad

  27. KM1- S/N 37887 Functional & VIH/VILPrior to Burn In Reason for investigation: Functional & VIH/VIL Failure History after Programming • KM1 first test was done at -55ºC vs. room temperature in error • First test at -55ºC ATE test failed functional and VIH/VIL Current Actions • Failure analysis on hold pending investigator availability

  28. KM1- S/N 37858 Array Shift register Post 250 hour Burn In Reason for investigation: Functional Failure History Following Programming • Passed all Tri-Temp testing prior to Burn In testing • Completed ATE room temperature after 50 hours Burn In • After 250 Hour HTOL failed functional Array Shift register test on ATE • Unit failed array_monitor and array_out signals • Unit failed 1MHz and 50MHz functional tests • Tested on the bench • Failure isolated to array pattern generator instance using Silicon Explorer • This involves the shift register part of the pattern generator • Failure not dependent on frequency (tested from 500KHz to 15MHz)

  29. KM1- S/N 37858 Array Shift register Silicon Explorer failure capture • The following picture shows that the failure occurs between ShiftZ0Z_5 and ShiftZ0Z_6 output signals in the array_pat_inst • ShiftZ0Z_6 signal has a rising edge that occurs one clock cycle early • ShiftZ0Z_6 signal’s falling edge occurs at the correct time

  30. KM1- S/N 37858 Array Shift register Silicon Explorer reference capture • The following picture shows the ShiftZ0Z_5 and ShiftZ0Z_6 output signals in the array_pat_inst on a reference unit S/N 37955

  31. KM1- S/N 37858 Array Shift register Logical location of failure • Logic Diagram of the Array Pattern Generator • Failure occurs at ShiftZ0Z_6

  32. KM1- S/N 37858 Array Shift register Next Steps Current Actions • Failure analysis on-going Next Steps • 1st Manual Fuse Check of K-antifuse • 2nd If needed Manual Fuse Check other 3 antifuses in the data path net

  33. Anomaly Summary

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