Computer Systems Organization & Architecture Chapter 1 Part 4 Combinatorial Circuit Design

1. Computer Systems Organization & Architecture Chapter 1 Part 4 Combinatorial Circuit Design

2. Output a 0 or 1 based on the value of the input lines Majority wins Using MUXes:Majority Voting

3. Can implement a truth table by making the TT output the MUX input Implementing Truth Tableswith MUX 0 8x1 Mux 0 0 1 0 1 1 1 S2 S1 S0

4. Unfortunately, due to physical constraints, we need the fan-in of all circuits to be small So we need to implement this solution with 4x1 and 2x1 MUXes Use the technique learned earlier. Using MUXes:Majority Voting

5. Divide the table into two parts. Using MUXes:Majority Voting selector S2 is 0 4x1 Mux with selectors S1S0 Combine with a 2x1 Mux with selector S2 selector S2 is 1 4x1 Mux with selectors S1S0

6. Example: assume S2S1S0 are 110. Using MUXes:Majority Voting selectors S1S0 are 10 so choose line 3 selector S2 is 1 so chooses the bottom line, so output is 1 selectors S1S0 are 10 so choose line 3

7. Majority Voting 4x1 Mux 0 0 0 2x1 Mux 1 S1 S0 F 4x1 Mux 0 1 1 1 S2 S1 S0

8. Alternative design technique. Can double the size of the truth table that a given MUX can handle. Folding

9. Technique: For a function of n variables, connect the leftmost n–1 inputs xn-1, …,x1 to the select lines Divide the table into two-line sections and express f for each section as a function of the rightmost variable x0 Connect this value to the data input labeled with the combination xn,…,x1 for this section of the table. Folding

10. Technique: Folding 0 4x1 Mux 00 01 10 11 0 S0 F S0 S’0 S’0 1 S2 S1 1

11. Example: microprocessor system with 256 bytes of memory. Assume made of one 256 x 8 RAM chip (256 8-bit registers). To address this need 8 address lines (addresses 00 to FF) Will discuss the configuration of RAM chips later. Address Decoding

12. Address Decoding Data lines not shown Active low enable input.

13. Goal: increase RAM to 1K. Requires four 256 x 8 RAM chips. Addressing: Address Decoding

14. C0 Chip Size Is 4 bytes C1 C2 C3 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11 Example with 4 chips, each storing 4 bytes. 16 total bytes so need 4 address bits

15. Lower 8 address lines (A7 - A0) run to the address lines on each of the four chips These select one of the 256 locations in each RAM chip Highest 2 address lines (A8 and A9) determine which of the four RAM chips to access. Use these lines as select-line inputs on a 2-to-4 decoder. One of the four outputs will go low based on the two address lines. Connect the output lines to the enable input on the RAM chip Note that decode output is active low. Address Decoding

16. Address Decoding

17. Converts From the binary representation of a decimal digit (0000 to 1001) to the signals needed to show the digit on a 7-segment LED display Uses only combinatorial logic gates See next slide for LED, segments, and TT Binary Coded Decimal (BCD) decoder

18. Page 30, Figure 1.22

19. Design is 7 distinct circuits, one for each segment a through d. Design process for each: Create a Karnaugh map with X3-X0 as inputs, value of segment as the cell value, Don’t care for rest of cells Segment a was given in an earlier slide. Segments b and c and their implementations are on next slides BCD decoder

20. Karnaugh Maps for BCD decoder

21. Segments b & c of BCD decoder

22. For many applications, better to use active low LED displays 0 lights the display, 1 blanks the display To implement: Complement every entry in the truth table Construct a K-map for each segment Alternative: invert the outputs derived for the active high case May result in more complex circuitry than necessary BCD decoder

23. Why are LEDs usually active low? Both active high and active low configurations shown on next slide LED is lit if current is flowing through it This happns if there is a potential different, I.e., voltage at the input of LED is greater than voltage at output Typically, a logic 1 corresponds to a voltage of 5V in TTL digital logic A logic 0 corresponds to 0V Input voltage must be greater or equal to output voltage for LEDs to be lit. BCD decoder

24. Page 32, Practical Perspective: Figure 1A Figure a. Active high LED. Lit when logic input is 1. When logic input is 0, both input and output are at 0V, no potential difference and no current. Figure b. Active low LED. Lit when logic input is 0. When logic input is 1, both input and output are at 5V, no potential difference and no current.

25. Reason 1: source of current In active high LED, current to light the LED is sourced by the logic component It generates the logic 1. In active low LED, current to light the LED is sourced by circuit’s power supply Logic component sinks the current It is preferable to light the LEDs directly from the power supply rather than a logic component. Active Low BCDs

26. Reason 2: speed the logic signal to light the LED often comes from the output of a gate. If active high, usually AND or OR gate If active low, usually NAND or NOR gate NAND and NOR are faster. Active Low BCDs

27. Input: four 4-bit values Output: the input values in descending order Method: similar to a bubble sort: Compare adjacent entries and swap them if necessary Building blocks: the compare-and-swap module See next slide Two data inputs Compares them using the 4-bit comparator described in part 3 of the slides Data Sorter

28. 2-input compare-and-swap module All lines except the selector line of the MUXes are 4 bits Comparator

29. The comparator output X > Y used to select one of the two inputs to the upper multiplexer. If X > Y, selects the X input and passes it through If X < Y or X = Y, selects the Y input and passes it through Result: the output is the greater of X and Y The comparator X < Y output uses similar logic to output the smaller of X and Y Note that the input and output is 4-bits. Equivalent to using 4 1-bit multiplexers in parallel. All 4 would share the same control input Use this building block to construct a network to sort the input values. See next slide. Data Sorter

30. Four-input Data Sorter