NoC

2. NoC • General concepts • Andreas Ehliar - Per Karlström

3. Outline • Background • Some Implementations • Design Issues / Tools • Example Application • Conclusions

4. Current Situation Transistors Time

5. Current Situation IP IP IP IP IP IP IP IP IP IP IP

6. NOC implementations • SoCBUS • xPipes • Pleiades • Eclipse • (FPGA)

7. SoCBUS

8. Pipes

9. Pleiades ALU MEM ALU DSP FPGA MAC MEM MAC etc.

10. Eclipse

11. FPGA

12. Homogenous NoC FU FU FU FU FU

13. Heterogeneous NoC FU DSP FU FU MUL FU FU ALU

14. Heterogeneous NoC DSP FU FU MUL FU FU ALU

15. Quality of Service • Guaranteed latency • Guaranteed bandwidth • Correctness

16. Design Issues - Signaling V t

17. Design Issues - Clocking ALU MEM DSP FPGA

18. Design Issues - Architecture FU FU FU FU FU FU FU FU FU

19. Design Issues - Architecture FU FU FU FU FU FU FU FU FU

20. Design Issues- Errors Cost Error detection Error correction Ne/Np

21. Design Issues - Flow Control

22. Design Issues - Effect of Design Silicon Transistor Gate RTL Architecture Algorithm

23. Design Issues - Power Control

25. Design Issues - Long Wires • Solving the global interconnect mess • Delay • Bit errors • Repeaters • Clock domains • Create one optimized solution that can be reused

26. Design Issues - Long Wires • Add flip flops to increase clock frequency • What about ACKs? NoC Router NoC Router

27. Design Issues - Long Wires • Add flip flops to increase clock frequency • What about ACKs? NoC Router NoC Router What about bit errors?

28. Design Issues - Long Wires • Bit errors on long wires will not be avoidable in the future • Use error correcting codes • Disadvantage: More wires • Use parity bits to discover errors • Resend damaged packets • No longer possible to guarantee real-time performance

29. Design Issues - Long Wires • Possibility to create heavily optimized solution • Low voltage signaling • Advanced symbol encoding/decoding • Wave pipelining

30. Design Issues - Long Wires • High performance interconnect through wave pipelining • Need very careful analysis NoC Router NoC Router NoC Router NoC Router

31. Design Issues - Long Wires • Wave pipelining performance • 3.45 Ghz signaling on one bit line in 0.25 um • More energy efficient than regular pipeline • Faster than regular pipeline • Disadvantage • Much harder to test/verify

32. System design • Typical tools • Simulator • Network generator

33. System design • What I would want • Graphical frontend to design NoC • C and RTL models of the finished NoC • C API to create C level models of the NoC • Mix C and RTL models in RTL simulator • And of course...

34. System design IP cores

35. Example: Core Router • SoCBUS Simulation • Study of 16 port core router on a chip • 16 x 10 Gigabit Ethernet Ports • Prove feasibility of using SoCBUS

36. Example: Core Router IPP FT PB CPU MU OPP

37. Example: Core Router • IPP (Input Packet Processor) • Receive packet from network • Validate Packet/Filter packet • Send lookup request to forwarding table • Send packet to Packet Buffer • FT (Forwarding Table) • Get IP address from IPP • Perform Lookup and send the output port to the packet buffer • OPP (Output Packet Processor) • Send packet to Network

38. Example: Core Router • PB (Packet Buffer) • Responsible for packet buffering • Buffers packets until output port information is received from the forwarding table • MU (Multicast Unit) • Handle multicast packets • CPU

39. Example: Core Router • Data flow for a single packet Forwarding Table Input Packet Processor Packet Buffer Output Packet Processor

40. Example: Core Router • Assumptions: • Each link can transfer 64 bits each clock cycle • SoCBUS can be clocked at 1.2 Ghz • Packet buffers are “large enough”

41. Example: Core Router • Results for “Internet Mix” packet sizes

42. Example: Core Router • Results for minimum size packets

43. Example: Core Router • Network utilization

44. Example: Core Router • Bottleneck in forwarding table access • Current version of SoCBUS creates a virtual circuit for each request • Proposal: Extend SoCBUS • Reliable delivery of small (64 bit or less) packets without setting up a virtual circuit

45. Example: Core Router • Conclusion on this application example • Initial concept seems to work in simulation • Current work: • Master thesis to test concept in an FPGA

46. Our Reflections • Many papers use routers for each connection core • Not every IP core has to have a NoC Uplink • Probably better to use local shared buses with a common NoC Uplink • On the Internet, terminals are not connected directly to routers • Hard to design a network if the traffic is unknown

47. Our Reflections • Research on how to improve NoCs can often be used to improve non-NoC based designs • Communication over long distances • Improved crossbars • It will be hard to guarantee real-time performance on NoCs

48. Conclusions • NoC seems to be a reasonable tradeoff • Similar to how standard cells make it easier to design chips • No industry usage (yet?) • As yet, no killer application has been demonstrated • Next level of abstraction • IP centric design

49. Questions/Discussion • Will future chips have communication patterns favoring NoCs?

50. References • Networks on chips: a new SoC paradigm Benini, L.; De Micheli, G.; Computer , Volume: 35 , Issue: 1 , Jan. 2002 Pages:70 - 78 • Powering networks on chips Benini, L.; De Micheli, G.; System Synthesis, 2001. Proceedings. The 14th International Symposium on, 30 Sept.-3 Oct. 2001 Pages:33 – 38 • Addressing the system-on-a-chip interconnect woes through communication-based design Sgroi, M.; Sheets, M.; Mihal, A.; Keutzer, K.; Malik, S.; Rabaey, J.; Sangiovanni-Vincentelli, A.; Design Automation Conference, 2001. Proceedings , 18-22 June 2001 Pages:667 - 672 • On-chip networks: a scalable, communication-centric embedded system design paradigm Henkel, J.; Wolf, W.; Chakradhar, S.; VLSI Design, 2004. Proceedings. 17th International Conference on , 2004 Pages:845 - 851 • Design of a Core Router using the SoCBUS On-chip Network; Jimmy Svensson; LiTH-ISY-EX-04/3562-SE; LiTH