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MODIP: Design flow Introduction. Joaquin Canovas. Outline. About myself. PROCESS OVERVIEW. VERIFICATION. INTEGRATION. SYNTHESIS. BACKEND. SOFTWARE. WORKING ENVIRONMENT. About myself. Process overview. Requirements, customers/Standard/… ( PM , SM , SA )
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MODIP: Design flow Introduction Joaquin Canovas
Outline • About myself • PROCESS OVERVIEW • VERIFICATION • INTEGRATION • SYNTHESIS • BACKEND SOFTWARE • WORKING ENVIRONMENT
Process overview • Requirements, customers/Standard/… (PM, SM, SA) • FSMs + Datapaths + ALUs + Memories + … = Block • Block Verification = Is the design compliant with the specs? • Block1+Block2+…+BlockN = Subsystem / Integration • Integration correct? +Additional tests at sybsystem. • Physical implementation.
verification • Verification, why? - The cost of fixing a bug grows exponentially with the stage at which it is detected/fixed • Examples: • Block Verification: • Statement of compliance/implementation • Subsystem Verification: • Connections, data transfers, interfaces, address mapping… • DFT: • Can the manufactured silicon be tested? • Static Timing Analysis: • Delay calculations/simulations. Circuit frequency limitation. • Electrical verification…
INTEGRATION • Block Diagram:
Synthesis • RTL (HDL) 2 GATES (Verilog): • Synthesis: • RTL, Verilog, SystemC,… NETLIST • Design “description” Design Implementation • Floorplan layout: Placing the design and routing.
BACKEND • FLOORPLAN LAYOUT (BE): • Placing the design and routing. • Real design: • Block diagram:
Software • Examples: • SYSTEM SIMULATION: • Algorithm development/simulation, bit widths, performance,… • VERIFICATION PLATFORMS: • Need to start SW development as soon as possible • Radio Access Technology (RAT) SW: • Network Signaling (NSSW)
Working environment SA PM & SM Requirements Design Verification Phys. Implementation Project Office HW DESIGN BLOCK VER INTEG. SS. VER RTL2GATES BE