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SOC Encounter v4.1

SOC Encounter v4.1. Speaker: I–Wei Lai Advisor ： Tzi-Dar Chiueh Mar. 14, 2005. Outline. Introduction of SOCE v4.1 New Functions inside SOCE v4.1 Design Flow Conclusion Reference. Introduction of SOCE v4.1. Introduction of SOCE v4.1(1/2).

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SOC Encounter v4.1

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  1. SOC Encounter v4.1 Speaker: I–Wei Lai Advisor：Tzi-Dar Chiueh Mar. 14, 2005

  2. Outline • Introduction of SOCE v4.1 • New Functions inside SOCE v4.1 • Design Flow • Conclusion • Reference

  3. Introduction of SOCE v4.1

  4. Introduction of SOCE v4.1(1/2) • SOC EncounterTM is a EDA tool develop by Cadence • From Gate level to GDSII • Support 50+ million gate design at 180nm and below

  5. Introduction of SOCE v4.1 (2/2) • SOCE is a platform and integrates • First Encounter Ultra • CeltIC • NanoRoute • SignalStorm NDC • VoltageStorm • Fire& Ice QXC

  6. New Functions inside SOCE v4.1

  7. Import data SVP Floorplan Stramout Timing analysis powerplan power analysis *CTS synthesis placement Timing Optimization Design Flow Library User data Route *.gds *.DEF

  8. Silicon Virtual Prototype • Providing quick feedback on the design performance • Use Trial Route to build up SVP • Designer can perform • timing analysis (SignalStorm NDC) • power analysis (VoltageStorm) immediately after each step

  9. Trial Route • Quick routing for estimating routing-related congestion and capacitance values • Does not guarantee DRC-clean routing • Does not perform signal integrity analysis • Use WRoute or NRoute for final routing

  10. NanoRoute(1/2) • Nearnano effect • Wire delay • IR drop and SI effect • Suitable for • .13 technology • Chip more than 300K instances

  11. NanoRoute(2/2) • Supports • Timing issue • Signal integrity • Manufacturing Awareness • multi threading • Super threading

  12. Timing Optimization • Optimizing • Correct DRVs • Reduce total negative slack • Setup & hold time • Skew optimization * • Optimizing by using techniques • Adding buffers • Resizing gates • Restructuring the netlist • Remapping logics • Swapping pins

  13. Design Flow (Encounter V4.1)

  14. Operation condition Pin type Path Delay Timing constraint TCL format Requiring Data • Library • Physical Library(*.LEF) • Timing Library(*.LIB) • Capacitance Table • Celtic Library • Fire&Ice/VoltageStorm Library • User Data • Gate-Level netlist(*.v) • Timing constraints(*.sdc) • IO constraint(*.ioc)

  15. Environment Setting • Add • source /usr/cadence/SOC/CIC/soc.csh • source /usr/cadence/SOC/CIC/license.csh in your .cshrc • Start SOC Encounter • unix%encounter (don’t run in background mode)

  16. Import data Floorplan Stramout Route powerplan *CT synthesis placement *.gds *.DEF Design Flow Library User data

  17. GUI Design->Design Import…

  18. Import Design(1/3)

  19. Global nets Import Design(2/3)

  20. For more accuracy RC extraction (optional) For crosstalk analysis (optional) Save these steps into *.conf *Import Design(3/3)

  21. Save/Restore design • The temporal design can be save or restore at any point during the flow • *.enc

  22. Initial Floorplan view Flight lines Our design hard macro Floorplan->Global Net Connections…

  23. Global Connect 1a. VDD(VSS) 1b. VDD(VSS) 1c.Connect 1’b1(1’b0) to Global nets 2. VDD(VSS) 3. Add to List 4. Repeat 1a,b,c~3 six times

  24. FloorPlan(1/3) Row spacing >1 Row spacing =0

  25. Floorplan(2/3) –Place & *Place hard marco • Floorplan->Place Blocks/Modules->Place • *Select “Place hard macros inside modules” • Use • Floorplan->Edit Floorplan->Flip/Rotate Instances… • Floorplan->Set Block Placement Status… Set block state “pre-state”

  26. Floorplan(3/3) –move the block • Floorplan->Edit Block Halo initial move&rotate add block halo

  27. Powerplan(1/5)-Add Power Ring • Floorplan->Power planning->Add Rings Auto adjust spacing

  28. Powerplan(2/5) -Add Power Ring • Use Wire group prevent slot error • Route->SRoute, Select “Pad pins” connecting power ring to power pad The number of thin rings

  29. Powerplan(3/5)-interleave • Interleaving w/o interleaving

  30. Powerplan(4/5)-add power stripe • Floorplan ->Power Planning -> Add Stripes… • Select “Omit stripes inside block rings” at Advanced tab • Use wire group, too • Route>SRoute, select ”Stripes(unconnectd)” distance between adjacent stripe

  31. Powerplan(5/5)-add power stripe

  32. Placement • *Specify ScanChain First • Place->Place… select ”Medium effort” or “High effort”,

  33. *CT synthesis(1/3) • Clock->Create Clock Tree Spec… • Clock->Specify Clock Tree…

  34. The color means Phase delay Max/min path *CT synthesis(2/3) 3. Clock->Synthesize Clock Tree 4. Clock->Display->Display Clock Tree clk pad

  35. *CT synthesis(3/3) • Clock->Clock Tree Browser... • open Clock Tree Browser form • Show the detail clock info. and modify the clock tree

  36. Route(1/4)- power route & Add Filler • Route->SRoute…select ”Standard Cell pins ” • Key in • addIOFiller –cell <fillercellname> –prefix PFEED at command line • Fillercellname • PFEED<num> ex: PFEED50 PFEED5 PFEED01 • The number means the size of filler cell

  37. Route(2/4)- nRoute • Route->nRoute assign characteristics to special nets

  38. Route(3/4)-nRoute • SuperThreading • Use .rhosts to get the remote control Global route detail route Final report

  39. Route(4/4)- Add Core Filler • Place->Filler->Add Filler • Fillers are placed from large to small

  40. Final view

  41. Streamout • Design->Save->GDS • Design->Save->DEF

  42. SVP Timing analysis power analysis Timing Optimization Design Flow

  43. SVP • Build up SVP before t/p analysis • Place->Place, Select “Prototyping” • Route->Trial Route, select “Prototyping” Physical view Amoeba view

  44. Timing Analysis(1/2) • Timing->Extract RC… • Timing->Timing Analysis • Timing->Timing Debug->Slack Browser

  45. Timing Analysis(2/2) • Slack browser…

  46. Power Analysis(1/4) • Timing->Extract RC… • Power->Edit Pad Location

  47. Power Analysis(2/4) 3. Power->Edit Net Toggle Probability…

  48. Power analysis(3/4) VDD or VSS 4. Power->Power Analysis-> Statistical…

  49. Power analysis(4/4) • Read Pa.report • Power->Display->Display Rail analysis Result… IR drop EM

  50. Timing Optimization • Timing->Optimization

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