Digital Design with VHDL

1. Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi Email: amgh@mehr.sharif.edu

2. Concurrent Statements • Concurrent Signal Assignment • Component Instantiation Statement • Generate Statement • Process Statement • Block Statement • Concurrent Procedure Call Statement • Concurrent Assert Statement

3. Sequential Statements • Signal Assignment Statement • Variable Assignment Statement • IF Statement • Case Statement • Loop Statement • Wait Statement • Procedure Call Statement

4. Sequential Statements (cont.) • Next Statement • Exit Statement • Return Statement • Assertion Statement • Report Statement • Null Statement

5. Serial to Parallel (Entity) ENTITY s2p IS GENERIC (bps: INTEGER); PORT (s_in, rec : IN BIT; d_ready: BUFFER BIT; overrun, f_error: OUT BIT; p_out: OUT BIT_VECTOR(7 DOWNTO 0)); END s2p;

6. Serial to Parallel ARCHITECTURE w OF s2p IS BEGIN collect: PROCESS VARIABLE buff: BIT_VECTOR(7 DOWNTO 0); CONSTANT half: TIME :=(1000000.0/REAL(bps))/2.0*1 US; CONSTANT full: TIME :=(1000000.0/REAL(bps))/2.0*1 US; BEGIN WAIT UNTIL serial = ‘0’; WAIT FOR half; FOR count IN 0 TO 7 LOOP WAIT FOR full; buff(count) := serail; END LOOP;

7. Serial to Parallel IF serial = ‘0’ THEN f_error <= ‘1’; WAIT UNTIL serial = ‘1’; ELSE f_errro <= ‘0’; d_ready <= ‘1’; p_out <= buff; WAIT UNTIL rec = ‘1’; WAIT UNTIL rec = ‘0’; d_ready <= ‘0’; END IF; END PROCESS;

8. Serial to Parallel too_fast: PROCESS BEGIN IF d_ready = ‘1’ THEN WAIT UNTIL serial = ‘0’; IF d_ready = ‘1’ THEN overrun <= ‘1’; END IF; ELSE overrun <= ‘0’; END IF; WAIT ON d_ready; END PROCESS; END w;

9. Enumeration Type Declaration TYPE identifier IS (enumeration_literal { , enumeration_literal } ); enumeration_literal ::= identifier | character_literal

10. Moore FSM ENTITY moore IS PORT (x, clk: IN BIT; z: OUT BIT); END moore; ARCHITECTURE behavioral OF moore IS TYPE state IS (reset,got1,got10,got101,got1011); SIGNAL current : state := reset; BEGIN

11. Moore FSM (cont.) PROCESS BEGIN WAIT UNTIL clk = ‘1’ ; CASE current IS WHEN reset => IF x = ‘0’ THEN current <= got1; ELSE current <= reset; END IF; … END CASE; END PROCESS; z <= ‘1’ WHEN current = got1011 ELSE ‘0’; END behavioral;

12. Mealy FSM ARCHITECTURE behavioral OF mealy IS TYPE state IS (a, b, c); SIGNAL nxt, present : state := a; BEGIN -- of architecture PROCESS (clk) BEGIN IF (clk’EVENT AND clk = ‘1’) THEN present <= nxt; END IF; END PROCESS;

13. Mealy FSM (cont.) PROCESS (present , x) BEGIN z <= ‘0’; CASE present IS WHEN a => IF x = ‘0’ THEN nxt <= a ELSE nxt <= b; END IF; … END CASE; IF present = c AND x = ‘1’ THEN z <= ‘1’; END IF; END PROCESS; END behavioral ; -- of architecture

14. Array Type Declaration TYPE identifier IS ARRAY ( index {, index} ) OF element_subtype; Index ::= range | NATURAL RANGE <>

15. Array Type Example TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT; TYPE two_dim_bit IS ARRAY (0 TO 7, 15 DOWNTO 0) OF BIT; TYPE byte_memory IS ARRAY (NATURAL RANGE <>) OF BIT_VECTOR (7 DOWNTO 0);

16. Signal of Array Type Example SIGNAL a: BIT_VECTOR(1 TO 16); SIGNAL b: two_dim_bit; SIGNAL c: byte_memory(0 TO 1023); … c(0) <= a(1 TO 8); a(1 TO 8) <= b(1,15)&b(1,14)&b(1,13)&b(1,12)&b(1,11)&b(1,10)&b(1,9)&b(1,8); c(0) <= a(5 TO 12);

17. Specifying Radix SIGNAL a: BIT_VECTOR(7 DOWNTO 0); SIGNAL b: INTEGER; .. aa <= "10101111", B"0111_0101" AFTER 10 ns, x"F1" AFTER 50 ns; bb <= 100_789, 16#3F7# AFTER 30 NS, 4#103_2122# AFTER 100 ns;