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ECE 545—Digital System Design with VHDL Lecture 1

ECE 545—Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A – Combinational Logic Building Blocks. Lecture Roadmap – Combinational Logic. Basic Logic Review Basic Gates De Morgan ’ s Law Combinational Logic Building Blocks Multiplexers Decoders, Demultiplexers

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ECE 545—Digital System Design with VHDL Lecture 1

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  1. ECE 545—Digital System Design with VHDLLecture 1 Digital Logic Refresher Part A – Combinational Logic Building Blocks

  2. Lecture Roadmap – Combinational Logic Basic Logic Review Basic Gates De Morgan’s Law Combinational Logic Building Blocks Multiplexers Decoders, Demultiplexers Encoders, Priority Encoders Arithmetic circuits ROM. Implementing combinational logic using ROM. Tri-state buffers.

  3. Textbook References • Combinational Logic Review • Stephen Brown and ZvonkoVranesic, Fundamentals of Digital Logic with VHDL Design, 2ndor 3rd Edition • Chapter 2 Introduction to Logic Circuits (2.1-2.8 only) • Chapter 6 Combinational-Circuit Building Blocks (6.1-6.5 only) • ORyour undergraduate digital logic textbook (chapters on combinational logic)

  4. Basic Logic Review some slides modified from:S. Dandamudi, “Fundamentals of Computer Organization and Design”

  5. Basic Logic Gates (2-input versions)

  6. Simple logic gates AND  0 if one or more inputs is 0 OR  1 if one or more inputs is 1 NAND = AND + NOT 1 if one or more inputs is 0 NOR = OR + NOT 0 if one or more input is 1 XOR  1 if an odd number of inputs is 1 XNOR  1 if an even number of inputs is 1 NAND and NOR gates require fewer transistors than AND and OR in standard CMOS Functionality can be expressed by a truth table A truth table lists output for each possible input combination Basic Logic Gates Generalized

  7. Number of Functions • Number of functions • With N logical variables, we can define 22N functions • Some of them are useful • AND, NAND, NOR, XOR, … • Some are not useful: • Output is always 1 • Output is always 0 • “Number of functions” definition is useful in proving completeness property

  8. Complete Set of Gates • Complete sets • A set of gates is complete • if we can implement any logic function using only the type of gates in the set • Some example complete sets • {AND, OR, NOT} Not a minimal complete set • {AND, NOT} • {OR, NOT} • {NAND} • {NOR} • Minimal complete set • A complete set with no redundant elements.

  9. NAND as a Complete Set • Proving NAND gate is universal

  10. Logic Functions • Logic functions can be expressed in several ways: • Truth table • Logical expressions • Graphical schematic form • HDL code • Example: • Majority function • Output is one whenever majority of inputs is 1 • We use 3-input majority function

  11. Truth table A B C F 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Logical expression form F = A B + B C + A C Alternative Representations of Logic Function Graphical schematic form HDL code: F <= (A AND B) OR (B AND C) OR (A AND C) ;

  12. Boolean Algebra Boolean identities Name AND version OR version Identity x.1 = x x + 0 = x Complement x. x’ = 0 x + x’ = 1 Commutative x.y = y.x x + y = y + x Distribution x. (y+z) = xy+xz x + (y. z) = (x+y) (x+z) Idempotent x.x = x x + x = x Null x.0 = 0 x + 1 = 1

  13. Boolean Algebra (cont’d) • Boolean identities (cont’d) Name AND version OR version Involution x = (x’)’ --- Absorption x. (x+y) = x x + (x.y) = x Associative x.(y. z) = (x. y).z x + (y + z) = (x + y) + z de Morgan (x. y)’ = x’ + y’ (x + y)’ = x’. y’ (de Morgan’s law in particular is very useful)

  14. Alternative symbols for NAND and NOR

  15. Majority Function Using Other Gates • Using NAND gates • Get an equivalent expression A B + C D = (A B + C D)’’ • Using de Morgan’s law A B + C D = ( (A B)’. (C D)’)’ • Can be generalized • Example: Majority function A B + B C + AC = ((A B)’. (B C)’. (AC)’)’

  16. Majority Function Using Other Gates (cont'd) • Majority function

  17. Combinational Logic Building Blocks Some slides modified from:S. Dandamudi, “Fundamentals of Computer Organization and Design”S. Brown and Z. Vranesic, "Fundamentals of Digital Logic"

  18. Multiplexers • multiplexer • n binary inputs (binary input = 1-bit input) • log2n binary selection inputs • 1 binary output • Function: one of n inputs is placed onto output • Called n-to-1 multiplexer log2n selection inputs n inputs 1 output

  19. 2-to-1 Multiplexer s f s w w 0 0 0 0 f w 1 w 1 1 1 (b) Truth table (a) Graphical symbol w w 0 0 s s f w w f 1 1 (d) Circuit with transmission gates (c) Sum-of-products circuit Source: Brown and Vranesic

  20. 4-to-1 Multiplexer s 0 s s s f 1 1 0 w w 00 0 0 0 0 w 01 w 1 0 1 f 1 w 10 w 2 1 0 2 w 11 3 w 1 1 3 (a) Graphic symbol (b) Truth table s 0 w 0 s 1 w 1 f w 2 w 3 Source: Brown and Vranesic (c) Circuit

  21. Multi-bit 4-to-1 Multiplexer • When drawing schematics, can draw multi-bit multiplexers • Example: 8-bit 4-to-1 multiplexer • 4 inputs (each 8 bits) • 1 output (8 bits) • 2 selection bits • Can also have multi-bit 2-to-1 muxes, 16-to-1 muxes, etc. s 0 s s s f 1 1 0 w w 00 0 0 0 0 w 01 w 1 0 1 f 1 w 10 w 2 1 0 2 w 8 11 3 w 1 1 3 8 (a) Graphic symbol (b) Truth table

  22. 8-bit 4-to-1 Multiplexer s 0 s 1 w0(7) 00 w1(7) 01 f(7) w2(7) 10 11 w3(7) s 0 s An 8-bit 4-to-1 multiplexer is composedof eight [1-bit] 4-to-1 multiplexers s 0 1 s w0(6) 1 00 w1(6) w 00 01 0 = f(6) w w2(6) 01 10 1 f w 10 11 w3(6) 2 w 8 11 3 8 s 0 s 1 w0(0) 00 w1(0) 01 f(0) w2(0) 10 11 w3(0)

  23. Decoders • Decoder • n binary inputs • 2n binary outputs • Function: decode encoded information • If enable=1, one output is asserted high, the other outputs are asserted low • If enable=0, all outputs asserted low • Often, enable pin is not needed (i.e. the decoder is always enabled) • Called n-to-2n decoder • Can consider n binary inputs as a single n-bit input • Can consider 2n binary outputs as a single 2n-bit output • Decoders are often used for RAM/ROM addressing y w n 2 – 1 n-1 n n 2 inputs w outputs 0 y Enable En 0

  24. 2-to-4 Decoder w w y y y y En 1 0 3 2 1 0 w y 1 3 1 0 0 0 0 0 1 w y 0 2 0 1 0 0 1 0 1 y 1 1 1 0 0 1 0 0 y En 0 1 1 1 1 0 0 0 - - 0 0 0 0 0 (a) Truth table (b) Graphical symbol w 0 y 0 w 1 y 1 y 2 y 3 En Source: Brown and Vranesic (c) Logic circuit

  25. Demultiplexers • Demultiplexer • 1 binary input • n binary outputs • log2n binary selection inputs • Function: places input onto one of n outputs, with the remaining outputs asserted low • Called 1-to-n demultiplexer • Closely related to decoder • Can build 1-to-n demultiplexer from log2n-to-n decoder by using the decoder's enable signal as the demultiplexer's input signal, and using decoder's input signals as the demultiplexer's selection input signals. log2n selection inputs 1 input n outputs

  26. 1-to-4 Demultiplexer

  27. Encoders • Encoder • 2n binary inputs • n binary outputs • Function: encodes information into an n-bit code • Called 2n-to-n encoder • Can consider 2n binary inputs as a single 2n-bit input • Can consider n binary output as a single n-bit output • Encoders only work when exactly one binary input is equal to 1 w n 2 – 1 y n – 1 n n 2 outputs inputs y 0 w 0

  28. 4-to-2 Encoder w w w w y y 3 2 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 (a) Truth table w 0 w 1 y 0 w 2 y 1 w 3 (b) Circuit

  29. Priority Encoders • Priority Encoder • 2n binary inputs • n binary outputs • 1 binary "valid" output • Function: encodes information into an n-bit code based on priority of inputs • Called 2n-to-n priority encoder • Priority encoder allows for multiple inputs to have a value of '1', as it encodes the input with the highest priority (MSB = highest priority, LSB = lowest priority) • "valid" output indicates when priority encoder output is valid • Priority encoder is more common than an encoder w n 2 – 1 y n – 1 n n 2 outputs inputs y 0 w z "valid" output 0

  30. 4-to-2 MSB Priority Encoder w w w w y y z 3 2 1 0 1 0 0 0 0 0 - - 0 0 0 0 1 0 0 1 - 0 0 1 0 1 1 - - 0 1 1 0 1 - - - 1 1 1 1

  31. Single-Bit Adders • Half-adder • Adds two binary (i.e. 1-bit) inputs A and B • Produces a sum and carryout • Problem: Cannot use it alone to build larger adders • Full-adder • Adds three binary (i.e. 1-bit) inputs A, B, and carryin • Like half-adder, produces a sum and carryout • Allows building M-bit adders (M > 1) • Simple technique • Connect Cout of one adder to Cin of the next • These are called ripple-carry adders

  32. Half-Adder c x 2 1 HA x + y = ( c s )2 s y x y c s 0 0 1 1 0 1 1 0 0 1 0 1 0 0 0 1

  33. Full-Adder x cout 2 1 FA y x + y + cin = ( cout s )2 s cin cout s cin x y x s 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 y cin cout

  34. 16-bit Unsigned Adder 16 16 X Y + Cout Cin S 16

  35. Multi-Bit Ripple-Carry Adder A 16-bit ripple-carry adder is composed of 16 (1-bit) full adders Inputs: 16-bit A, 16-bit B, 1-bit carry in (set to zero in the figure below) Outputs: 16-bit sum S, 1-bit carry out Other multi-bit adder structures can be studied in ECE 645—Computer Arithmetic Called a ripple-carry adder because carry ripples from one full-adder to the next. Critical path is 16 full-adders.

  36. Comparator • Used two compare two M-bit numbers and produce a flag (M >1) • Inputs: M-bit input A, M-bit input B • Output: 1-bit output flag • 1 indicates condition is met • 0 indicates condition is not met • Can compare: >, >=, <, <=, =, etc. A > B? A M 1 if A > B 0 if A <= B B M

  37. Example: 4-bit comparator (A = B) A = B? A 4 1 if A = B 0 if A != B B 4

  38. 4x4-bit Unsigned Multiplier 4 4 a b * c U 8

  39. 4x4-bit Signed Multiplier 4 4 a b * c S 8

  40. Unsigned vs. Signed Multiplication Unsigned Signed 1111 1111 1111 1111 15 15 -1 -1 x x x x 11100001 225 00000001 1

  41. Quotient and remainder Given integers a and n, n>0 ! q, r  Z such that a = q n + r and 0  r < n a q = q – quotient r – remainder (of a divided by n) = a div n n a r = a - q n = a –  n = n = a mod n

  42. Rules of addition, subtraction and multiplication modulo n a + b mod n = ((a mod n) + (b mod n)) mod n a - b mod n = ((a mod n) - (b mod n)) mod n ab mod n = ((a mod n)  (b mod n)) mod n

  43. Logical Shift Right A(1) A(0) A(3) A(2) 4 A A >>1 L C C 4 ‘0’ A(3) A(2) A(1)

  44. Arithmetic Shift Right A(1) A(0) A(3) A(2) 4 A A >>1 A C C 4 A(3) A(3) A(2) A(1)

  45. Fixed Rotation A(3) A(2) A(1) A(0) 4 A A <<< 1 C C 4 A(2) A(1) A(0) A(3)

  46. 8-bit Variable Rotator Left 8 A 3 A <<< B B C 8

  47. Read Only Memory (ROM) ROM ADDR DOUT n m

  48. Implementing Arbitrary Combinational LogicUsing ROM ROM ADDR DOUT 1 5

  49. Tri-state Buffer e x f e = 0 (a) A tri-state buffer x f e = 1 f e x x f 0 0 Z 0 1 Z (b) Equivalent circuit 1 0 0 1 1 1 (c) Truth table

  50. Four types of Tri-state Buffers

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