Understanding CPU Organization & Architecture

1. TK 2123COMPUTER ORGANISATION & ARCHITECTURE Lecture 5: CPU and Memory

2. Contents • This lecture will discuss: • Computer Systems Organisation. • Instruction Execution. • Design Principles for Modern Computers. Prepared by: Dr Masri Ayob - TK2123

3. Program Concept • Hardwired systems are inflexible • General purpose hardware can do different tasks, given correct control signals • Instead of re-wiring, supply a new set of control signals Prepared by: Dr Masri Ayob - TK2123

4. What is a program? • A sequence of steps • For each step, an arithmetic or logical operation is done • For each operation, a different set of control signals is needed Prepared by: Dr Masri Ayob - TK2123

5. Function of Control Unit • For each operation a unique code is provided • e.g. ADD, MOVE • A hardware segment accepts the code and issues the control signals • We have a computer! Prepared by: Dr Masri Ayob - TK2123

6. Components of Computer • Central Processing Unit (CPU) has: • The Control Unit (CU) • the Arithmetic and Logic Unit (ALU). • Data and instructions need to get into the system and results out • Input/output • Temporary storage of code, data and results is needed • Main memory Prepared by: Dr Masri Ayob - TK2123

7. Central Processing Unit The organisation of a simple computer with one CPU and two I/O devices Prepared by: Dr Masri Ayob - TK2123

8. CPU Organization The data path of a typical Von Neumann machine. Prepared by: Dr Masri Ayob - TK2123

9. Components of the CPU • The arithmetic/logic unit is the component of the CPU where data is held temporarily and where calculations take place. • The control unit controls and interprets the execution of instructions . • The control unit determines the particular instruction to be executed by reading the contents of a program counter (PC), sometimes called an instruction pointer, which is a part of the control unit. Prepared by: Dr Masri Ayob - TK2123

10. Components of the CPU • Normally, instructions are executed sequentially. • The sequence of instructions is modified by executing instructions that change the contents of the program counter. • A Memory Management Unit within the control unit supervises the fetching of instructions and data from memory. Prepared by: Dr Masri Ayob - TK2123

11. The Concept Of Registers • A register is a single, permanent storage location within the CPU used for a particular, defined purpose. • A register is used to hold a binary value temporarily for storage, for manipulation, and/or for simple calculations. • Each register is wired within the CPU to perform its specific role. • each register serves a particular purpose. • The register’s size, the way it is wired, and even the operations that take place in the register reflect the specific function that the register performs in the computer. Prepared by: Dr Masri Ayob - TK2123

12. The Concept Of Registers • They are not addressed as a memory location, but instead are manipulated directly by the control unit during the execution of instructions. • They may be as small as a single bit or as wide as several bytes, ranging usually from one to 128 bits. • A register may hold: • data being processed, • an instruction being executed, • a memory or I/O address to be accessed, • or even special binary codes used for some other purpose. • Some registers serve many different purposes, while others are designed to perform a single, specialised task. Prepared by: Dr Masri Ayob - TK2123

13. The Concept Of Registers • Registers are basic working components of the CPU. • The control unit contains several important registers: • the program counter (PC) register holds the address of the current instruction being executed. • The instruction register (IR) holds the actual instruction being executed currently by the computer. • The memory address register (MAR) holds the address of a memory location. • The memory data register (MDR), sometimes known as the memory buffer register, will hold a data value that is being stored to or retrieved from the memory location currently addressed by the memory address register. Prepared by: Dr Masri Ayob - TK2123

14. The Concept Of Registers • The CU also contain several 1-bit registers, sometimes known as flags, that are used to allow the computer to keep track of special conditions such as: • arithmetic carry and overflow, • power failure, and internal computer error. • Usually, several flags are grouped into one or more status registers. Prepared by: Dr Masri Ayob - TK2123

15. The Concept Of Registers • Most registers support four primary types of operations: • Registers can be loaded with values from other locations, in particular from other registers or from memory locations. • Data from another location can be added to or subtracted from the value previously stored in a register, leaving the sum or difference in the register. • Data in a register can be shifted or rotated right or left by one or more bits. • The value of data in a register can be tested for certain conditions, such as zero, positive, negative, or too large to fit in the register. Prepared by: Dr Masri Ayob - TK2123

16. THE MEMORY UNIT • The memory address register (MAR) and the memory data register (MDR), act is an interface between the CPU and memory. • The MDR is called the memory buffer register by some computer manufacturers. • Each cell in the memory unit holds one bit of data. • The cells are organized in rows. • Each row consists of a group of one or more bytes. • In modern computers, it is common to address eight bytes at a time to speed up memory access between the CPU and memory. Prepared by: Dr Masri Ayob - TK2123

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18. THE MEMORY UNIT • The MAR holds the address in the memory that is to be “opened” for data. • The MAR is connected to a decoder that interprets the address and activates a single address line into the memory. • The MDR is designed such that it is effectively connected to every cell in the memory unit. • Each bit of the MDR is connected in a column to the corresponding bit of every location in memory. • The addressing method assures that only a single row of cells is activated at any given time. • Only one memory location is addressed at any one time. Prepared by: Dr Masri Ayob - TK2123

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20. Memory Capacity • The number of bits in the MAR determines how many different address locations can be decoded. • For a MAR of width k bits, the number of possible memory addresses is M = 2k • For example: A 32-bit memory address allows a memory capacity of 4 gigabytes (GB) Prepared by: Dr Masri Ayob - TK2123

21. Memory Capacity • The size of the word to be retrieved or stored in a single operation is determined by the size of the MDR and by the width of the bus connecting memory to the CPU. • In most modern computers, data and instructions found in memory are addressed in multiples of 8-bit bytes. • the MDR is usually designed to retrieve the data or instruction(s) from a sequence of several successive addresses all at once, and the MDR will be several bytes wide. Prepared by: Dr Masri Ayob - TK2123

22. Instruction Cycle • Two steps: • Fetch • Execute Prepared by: Dr Masri Ayob - TK2123

23. Fetch/Execute Cycle • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC • Unless told otherwise • Instruction loaded into Instruction Register (IR) • Processor interprets instruction and performs required actions. • If instructions uses word in memory, fetch the word into CPU register. • Execute the instruction. Prepared by: Dr Masri Ayob - TK2123

24. Execute Cycle • Processor-memory • data transfer between CPU and main memory • Processor I/O • Data transfer between CPU and I/O module • Data processing • Some arithmetic or logical operation on data • Control • Alteration of sequence of operations • e.g. jump • Combination of above Prepared by: Dr Masri Ayob - TK2123

25. Design Principles for Modern Computers • All instructions directly executed by hardware • Maximise rate at which instructions are issued • Instructions should be easy to decode • Only loads, stores should reference memory • Provide plenty of registers Prepared by: Dr Masri Ayob - TK2123

26. Instruction-Level Parallelism • A five-stage pipeline • The state of each stage as a function of time. Nine clock cycles are illustrated Prepared by: Dr Masri Ayob - TK2123

27. Superscalar Architectures (1) Dual five-stage pipelines with a common instruction fetch unit. Prepared by: Dr Masri Ayob - TK2123

28. Superscalar Architectures (2) A superscalar processor with five functional units. Prepared by: Dr Masri Ayob - TK2123

29. Processor-Level Parallelism (1) An array of processor of the ILLIAC IV type. Prepared by: Dr Masri Ayob - TK2123

30. Processor-Level Parallelism (2) • A single-bus multiprocessor. • A multicomputer with local memories. Prepared by: Dr Masri Ayob - TK2123

31. Primary Memory: Memory Addresses (1) Three ways of organizing a 96-bit memory. Prepared by: Dr Masri Ayob - TK2123

32. Primary Memory : Memory Addresses (2) Number of bits per cell for some historically interesting commercial computers Prepared by: Dr Masri Ayob - TK2123

33. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Program • e.g. overflow, division by zero • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • from I/O controller • Hardware failure • e.g. memory parity error Prepared by: Dr Masri Ayob - TK2123

34. Program Flow Control Prepared by: Dr Masri Ayob - TK2123

35. Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program Prepared by: Dr Masri Ayob - TK2123

36. Transfer of Control via Interrupts Prepared by: Dr Masri Ayob - TK2123

37. Instruction Cycle with Interrupts Prepared by: Dr Masri Ayob - TK2123

38. Program TimingShort I/O Wait Prepared by: Dr Masri Ayob - TK2123

39. Program TimingLong I/O Wait Prepared by: Dr Masri Ayob - TK2123

40. Multiple Interrupts • Disable interrupts • Processor will ignore further interrupts whilst processing one interrupt • Interrupts remain pending and are checked after first interrupt has been processed • Interrupts handled in sequence as they occur • Define priorities • Low priority interrupts can be interrupted by higher priority interrupts • When higher priority interrupt has been processed, processor returns to previous interrupt Prepared by: Dr Masri Ayob - TK2123

41. Multiple Interrupts - Sequential Prepared by: Dr Masri Ayob - TK2123

42. Multiple Interrupts – Nested Prepared by: Dr Masri Ayob - TK2123

43. Time Sequence of Multiple Interrupts Prepared by: Dr Masri Ayob - TK2123

44. Connecting • All the units must be connected • Different type of connection for different type of unit • Memory • Input/Output • CPU Prepared by: Dr Masri Ayob - TK2123

45. Computer Modules Prepared by: Dr Masri Ayob - TK2123

46. Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing Prepared by: Dr Masri Ayob - TK2123

47. Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer Prepared by: Dr Masri Ayob - TK2123

48. Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control) Prepared by: Dr Masri Ayob - TK2123

49. CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts Prepared by: Dr Masri Ayob - TK2123

50. Buses • There are a number of possible interconnection systems • Single and multiple BUS structures are most common • e.g. Control/Address/Data bus (PC) • e.g. Unibus (DEC-PDP) Prepared by: Dr Masri Ayob - TK2123