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VHDL Synthesis for High-Reliability Systems

VHDL Synthesis for High-Reliability Systems. 2004 MAPLD International Conference Washington, D.C. September 7, 2004. Seminar Leaders And Practicing Design Engineers. Jonathan Alexander Actel Corporation Rod Barto NASA Office of Logic Design Melanie Berg Ball Aerospace

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VHDL Synthesis for High-Reliability Systems

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  1. VHDL Synthesis forHigh-Reliability Systems 2004 MAPLD International Conference Washington, D.C. September 7, 2004

  2. Seminar LeadersAnd Practicing Design Engineers Jonathan Alexander Actel Corporation Rod Barto NASA Office of Logic Design Melanie Berg Ball Aerospace Jeff Cotner NASA Johnson Space Center Marty Fraeman Applied Physics Laboratory Rich Katz NASA Office of Logic Design Igor Kleyner NASA Office of Logic Design

  3. Training vs. Education • The NASA Office of Logic Design works to educate design engineers, not train them. • Training promotes rote responses • Education promotes thinking and the ability to adapt to and cope with new situations. • Hence, MAPLD hosts seminars and not training sessions.

  4. Design Seminars • The field is complex and dynamic and most definitely not static. • Most examples are from or are derived from actual flight designs and are not academic exercises. • Many ways to accomplish functions, some better than others, often depending on the situation. • Contribute: Discuss the topics presented, disagree with them, present interesting cases you wish to share, and present better ideas. • Do not sit there quietly and expect to be treated like a cocker spaniel being trained and drilled to emit Pavlovian responses in response to stimuli (bell for dogs, donuts for engineers).

  5. Material • Material will be made available on • CD-ROM • Hardcopy • klabs.org • All public domain, you may use the material as you wish.

  6. Barto's Law: Every circuit is considered guilty until proven innocent.

  7. A VHDL Synthesis Issue:Synchronization Circuits

  8. Intended CircuitSynchronizer with Leading Edge Detect

  9. VHDL Code entity EDGE_DETECT_SYNC is generic ( RESET_LEVEL : STD_LOGIC := '1' ); port ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; INPUT : in STD_LOGIC; LED_OUT : out STD_LOGIC; TED_OUT : out STD_LOGIC ); end EDGE_DETECT_SYNC; architecture BEHAVIORAL of EDGE_DETECT_SYNC is signal IN_BETWEEN : STD_LOGIC; signal DATA_OUT : STD_LOGIC; begin FF1 : process(RESET, CLK) begin if (RESET = RESET_LEVEL) then IN_BETWEEN <= '0'; elsif rising_edge(CLK) then IN_BETWEEN <= INPUT; end if; end process; FF2 : process(RESET, CLK) begin if (RESET = RESET_LEVEL) then DATA_OUT <= '0'; elsif rising_edge(CLK) then DATA_OUT <= IN_BETWEEN; end if; end process; LED_OUT <= (not DATA_OUT) and IN_BETWEEN; TED_OUT <= DATA_OUT and (not IN_BETWEEN); end BEHAVIORAL;

  10. Synthesized Circuit Not pleasant to read

  11. Enjoy your seminar!

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