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CSCI206 - Computer Organization & Programming

CSCI206 - Computer Organization & Programming. Machine Language. Revised by Alexander Fuchsberger and Xiannong Meng in spring 2019 based on the notes by other instructors. zyBook: 5.4 Lab 2 & Prelab 3 are due tomorrow!. Positional Number Systems. n-th digit base.

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CSCI206 - Computer Organization & Programming

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  1. CSCI206 - Computer Organization & Programming Machine Language Revised by Alexander Fuchsberger and Xiannong Meng in spring 2019 based on the notes by other instructors. zyBook: 5.4 Lab 2 & Prelab 3 are due tomorrow!

  2. Positional Number Systems n-th digit base Example: in base 10 (decimal)

  3. Common bases Decimal: b=10, digits={0,1,2,3,4,5,6,7,8,9} Binary: b=2, digits={0,1} Octal: b=8, digits={0,1,2,3,4,5,6,7} Hexadecimal: b=16, digits={0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}

  4. Conversion Shortcuts Binary <--> octal: each group of three binary digits gives a complete octal digit Binary <--> hexadecimal: each group of four binary digits gives a complete hex digit e.g., 111 010 1012 -> 7258 e.g., 3678-> 011 110 1112 e.g., 1 1101 01012 -> 1D516 e.g., 3A416-> 0011 1010 01002

  5. Endianness • The order in which bytes are stored in a multibyte word • big-endian: stored with the most significant bits first (natural order when read from left to right) • little-endian: stored with the least significant bits first (looks weird)

  6. Endian Examples The hexadecimal value 0x01020304 Big endian address 100 101 103 100 102 byte address Little endian address 100 101 103 100 102 byte address

  7. MIPS Endianness • MIPS ISA Supports either, depending on the configuration • the MIPS simulator MARS we will use uses the host endianness, in our case LITTLE

  8. MIPS Summary design principle 2: smaller is faster • 32-bit architecture • load-store memory system (RISC) • optimized for the common case • 64 possible instructions (Why? How many bits?) • 32 registers • arithmetic operations have 3 operands • 3 registers • or 2 registers and one immediate value

  9. Assembly vs Machine Language 00000000 <main>: 0: 27bdffe0 addiu sp,sp,-32 4: afbf001c sw ra,28(sp) 8: afbe0018 sw s8,24(sp) c: 03a0f021 move s8,sp 10: 3c020000 lui v0,0x0 14: 24440000 addiu a0,v0,0 18: 24050201 li a1,513 1c: 240601e0 li a2,480 20: 0c000000 jal 0 <main> Machine (byte) code Assembly language code (text)

  10. MIPS Machine Language • a machine instruction always begins with the opcode 32-bit instruction

  11. Registers Come next • Most instructions operate on registers • the JUMP instructions do not! • Others access 2 or 3 registers • There are 32 registers in MIPS • how many bits are needed to specify a register?

  12. MIPS Machine Language Design Principle 3: Good design demands good compromises. • Three different types of instructions specified in opcode • R-type: registers are operands • I-type: registers and immediate value • J-type: jump instructions

  13. 1. Arithmetic (R-type) instructions 32 bits • opcode = basic operation (arithmetic = 0) • rs = first source register • rt = second source register • rd = destination register • shift amount = used for binary shift instruction • function = which arithmetic operation to perform (sent to the ALU) (e.g., add = 0x20, addu = 0x21...

  14. R-type example add $v0, $v0, $a0

  15. R-type example not used for add, set to 0 add $v0, $v0, $a0 add = 0x20 arithmetic = 0

  16. R-type example not used for add, set to 0 add $v0, $v0, $a0 add = 0x20 arithmetic = 0

  17. R-type example add $v0, $v0, $a0

  18. R-type example add $v0, $v0, $a0

  19. R-type example add $v0, $v0, $a0 ?? (hex value)

  20. R-type example add $v0, $v0, $a0 0x00441020

  21. 2. Immediate (I-Type) Instruction • R-type is used when there are three operands. • Many times we have a constant or immediate operand. • In this case that immediate value is included in the instruction.

  22. Immediate (I-Type) Instruction • Small constants are used frequently by programs • I-type instructions encode a 16-bit signed value to be used by the instruction

  23. I-Type example addi $s0, $s1, 40

  24. I-Type example addi $s0, $s1, 40 8 40

  25. I-Type example addi $s0, $s1, 40 16 17

  26. I-Type example addi $s0, $s1, 40 ?? (hex value)

  27. I-Type example addi $s0, $s1, 40 0x22300028

  28. 3. Jump (J-type) instruction • This instruction just tells the CPU to fetch the next instruction from a different location. • That location is encoded as an unsignedimmediate value in the instruction.

  29. J-type Example j MAIN ; assume MAIN = 0x400010 2

  30. J-type Example j MAIN ; assume MAIN = 0x0400010 2 0x0400010 is a byte address, but in MIPS instructions must be word aligned. So the lower 2 bits of the byte address must be 00. Therefore we omit them to save space in instruction! (making the 26-bit instruction effectively 28-bits!)

  31. J-type Example j MAIN ; assume MAIN = 0x0400010 2 0x0100004 removing the lower 2 bits of 0x0400010 is the same as dividing by 4 (shift right by 2), so the encoded value is 0x0100004.

  32. J-type Example j MAIN # assume MAIN == 0x400010 ?? (hex value)

  33. J-type Example 6 bit op-code: 0000 10 26 bit address : 0x0100004 which is 00 0001 0000 0000 0000 0000 0100 Putting two together: 0000 1000 0001 0000 0000 0000 0000 0100 Or 0x08100004

  34. J-type Example j MAIN ; assume MAIN == 0x400010 0x08100004

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