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LAD[31:0]

General Interconnection design. PCI R Reg. PCI W Reg. PCI R/W Reg. MB R Reg. MB W Reg. Mux. 32. LAD[31:0]. MB R/W Reg. PCI R /MB R Reg. 128. MBD[127:0]. PCI R /MB W Reg. PCI R /MB R/W Reg. PCI W /MB R Reg. PCI W /MB W Reg. Mux. Mux. PCI W /MB R/W Reg. Mux. PCI R/W /MB R Reg.

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LAD[31:0]

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  1. General Interconnection design PCI R Reg PCI W Reg PCI R/W Reg MB R Reg MB W Reg Mux 32 LAD[31:0] MB R/W Reg PCI R /MB R Reg 128 MBD[127:0] PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB R Reg PCI W /MB W Reg Mux Mux PCI W /MB R/W Reg Mux PCI R/W /MB R Reg PCI R/W /MB W Reg Mux PCI R/W /MB R/W Reg Mux

  2. 10 I/O Control Register 16 PCI Translation Base 16 MBus Upper Memory Address 16 MBus Lower Memory Address 16 MBus Translation Base 16 MBus Error Register Data Busses 32 PIO PCI to MB register 128 32 LAD[31:0] 128 PIO MB to PCI register Mux Broadcast Status Register 32 32 Crate Master Register 32 Internal Control Register Internal Request Register 32 128 MBD[127:0] 32 Internal Test Register 8 User Output Register User Input Register 8 Geographic Address Register 32 32 Mapper Array 128 Data FIFO 32 10 Address FIFO 32 PCI In Address Register PCI Out Address Register 32

  3. Memory Magic Bus Local bus Group Function Offset Type Width (bits) Depth (Words) accesses Base Address Width (bits) Depth (Words) accesses I/O Control Register 0x0000 Register LBA 0 I/O Control None 10 b 1 R/W PCI Translation Base 0x0010 Register LBA 0 None 16 b 1 R/W MBus Upper Memory Address 0x0014 Register LBA 0 None 16 b 1 R/W MBus Lower Memory Address 0x0018 Register LBA 0 PIO Configuration None 16 b 1 R/W MBus Translation Base 0x001C Register LBA 0 None 16 b 1 R/W MBus Error Register 0x0020 Register LBA 0 None 16 b 1 R/W PIO PCI to MB register win A/B ? Register 128 b 1 R LBA 1/2 32 b 1 W PIO Transfers PIO MB to PCI register ? Register 128 b 1 W LBA 1 32 b 1 R Broadcast Status Register 0x010C Register LBA 0 None 32 b 1 R Crate Master Register 0x0110 Register LBA 0 None 32 b 1 R/W Scaler Register 0x0114 Register LBA 0 None 32 b 1 R/W Internal Control Register 0x0130 Register LBA 0 None 32 b 1 R/W TSI Registers Internal Request Register 0x0134 Register LBA 0 None 32 b 1 R None 32 b 1 R/W Internal Test Register 0x013C Register LBA 0 User Output Register 0x0140 Register None 8 b 1 R/W LBA 0 0x0144 Register None 8 b 1 R User Input Register LBA 0 0x0148 Register None 32 b 1 R Geographic Address Register LBA 0 0x1000 RAM None 32 b R/W Mapper Registers Mapper Array LBA 0 0x400 Data FIFO ? FIFO 128 b 0x1000 W LBA 0 32 b 0x4000 R Data storage Address FIFO ? FIFO 10 b 0x1000 W LBA 0 10 b 0x1000 R

  4. 10 I/O Control Register 16 PCI Translation Base 16 MBus Upper Memory Address 16 MBus Lower Memory Address 16 MBus Translation Base 16 MBus Error Register Data Busses 32 PIO PCI to MB register 128 32 LAD[31:0] 128 PIO MB to PCI register 32 Broadcast Status Register 32 32 Crate Master Register 32 Scaler Register 32 Internal Control Register 128 MBD[127:0] Internal Request Register 32 32 Internal Test Register 8 User Output Register User Input Register 8 Geographic Address Register 32 32 Mapper Array 128 Data FIFO 32 10 Address FIFO 32 PCI In Address Register PCI Out Address Register 32

  5. fifo_full XCV405E mbd<127..0> fifo_empty mba<31..0> dma_access mod_done<18..0> ecl_access ev_loaded<3..0> mb_access n_bossreq pci_access DISPLAY n_dstrobe plx_access n_bossin vme_access bossgrin n_bossout vme_activity bossgrout n_ddonein mb_clk_in doneout gmb_clk_in n_ddoneout pci_clk_in CLOCK n_rd_wr gpci_clk_in MAGIC BUS n_startload n_bufin1 n_vme_rst_out n_bufin0 n_vme_rst_in n_bufout1 n_sw_rst_off RESET n_bufout0 n_sw_rst_on fifoemptyin n_led_reset n_fifoemptyout n_resetin n_ads n_resetout ale n_mbmaster n_bigend n_crmaster n_blast n_mben breqi n_mbdatdir breqo n_mbadddir n_bterm n_den vbd_start_req dmpaf_eot vbddone dp<3..0> l2_answer_ready n_dt_r ext_tsi_int_req lad<31..0> j2_resv_out<7..0> n_lbe<3..0> TSI j2_resv_in<7..0> lhold n_gap lholda LOCAL BUS n_ga<4..0> n_lw_r test_out<3..0> n_lserr n_ready tsi_out<31..0> n_wait n_linto test_pt<31..0> n_dack<1..0> TEST POINTS n_dreq<1..0> n_ccs lclk n_linti n_lb_reset useri_llocki usero_llocko pmereq

  6. fifo_full fifo_empty dma_access Rst & Display & Clock ecl_access mb_access XCV405E pci_access mbd<127..0> plx_access MAGIC BUS mba<31..0> vme_access Display management mod_done<18..0> ev_loaded<3..0> vme_activity n_bossreq n_dstrobe mb_clk_in n_bossin gmb_clk_in Address translator bossgrin pci_clk_in n_bossout gpci_clk_in Clock management Address decoder bossgrout n_ddonein n_vme_rst_out doneout n_vme_rst_in Add mapper n_ddoneout n_sw_rst_off n_rd_wr n_sw_rst_on n_startload n_led_reset n_bufin1 Reset management State machine n_bufin0 n_bufout1 Add translator n_bufout0 fifoemptyin n_fifoemptyout n_resetin n_ads n_resetout ale n_mbmaster n_bigend LOCAL BUS INTERFACE n_crmaster n_blast n_mben breqi n_mbdatdir breqo n_mbadddir n_bterm n_den dmpaf_eot dp<3..0> n_dt_r lad<31..0> n_lbe<3..0> lhold Address decoder PIO Block TSI Block lholda vbd_start_req n_lw_r vbddone n_lserr l2_answer_ready n_ready ext_tsi_int_req n_wait PIO registers TSI registers j2_resv_out<7..0> n_linto j2_resv_in<7..0> n_dack<1..0> State machine n_gap n_dreq<1..0> n_ga<4..0> n_ccs test_out<3..0> lclk n_linti State machine State machine tsi_out<31..0> n_lb_reset useri_llocki usero_llocko pmereq TEST POINTS test_pt<31..0>

  7. LOCAL BUS INTERFACE 32 PCI In Address Register pci_en_wr_mem_1 n_ads pci_ en_rd_mem_1 32 ale Address decoder pci_ en_buf_mem_1 PCI Out Address Register Combinatorial Logics lad<31..0> pci_ en_buf_mem_n data_in<31..0> pci_add_in<31..0> data_out<31..0> State machine pci_add_out<31..0> pci_ en_wr pci_ en_rd n_bigend n_blast breqi breqo n_bterm n_den dmpaf_eot int_pci_mb dp<3..0> n_dt_r int_mb_pci n_lbe<3..0> lhold dma_pci_mb lholda n_lw_r dma_pci_mb n_lserr n_ready n_wait n_linto n_dack<1..0> n_dreq<1..0> n_ccs lclk n_linti n_lb_reset useri_llocki usero_llocko pmereq

  8. MAGIC BUS INTERFACE Magic Bus In Address Register 32 mb_en_wr_mem_1 mb_en_rd_mem_1 32 Address decoder mb_en_buf_mem_1 Magic Bus Out Address Register Combinatorial Logics mba<31..0> mb_en_buf_mem_n mb_add_in<31..0> mb_add_out<31..0> State machine mb_en_wr mb_en_rd mod_done<18..0> ev_loaded<3..0> n_bossreq n_dstrobe int_pci_mb n_bossin bossgrin int_mb_pci n_bossout bossgrout n_ddonein dma_pci_mb doneout n_ddoneout dma_pci_mb n_rd_wr n_startload n_bufin1 n_bufin0 n_bufout1 n_bufout0 fifoemptyin n_fifoemptyout n_resetin n_resetout n_mbmaster n_crmaster n_mben n_mbdatdir n_mbadddir mbd<127..0> data_in<127..0> data_out<127..0>

  9. PIO Block PIO registers 10 I/O Control Register State machine 16 PCI Translation Base 16 MBus Upper Memory Address data_in<127..0> data_out<127..0> 16 MBus Lower Memory Address pci_en_wr_io_ctrl_reg pci_en_rd_io_ctrl_reg pci_en_wr_pci_trans_base pci_en_rd_pci_trans_base 16 MBus Translation Base pci_en_wr_mb_up_mem_add pci_en_rd_mb_up_mem_add pci_en_wr_mb_low_mem_base pci_en_rd_mb_low_mem_base 16 MBus Error Register pci_en_wr_mb_err_reg pci_en_rd_mb_err_reg pci_en_wr_pci_to_mb_reg pci_en_rd_pci_to_mb_reg 32 PIO PCI to MB register 128 mb_en_wr_pci_to_mb_reg mb_en_rd_pci_to_mb_reg pci_en_wr_mb_to_pci_reg pci_en_rd_mb_to_pci_reg 128 PIO MB to PCI register 32 mb_en_wr_mb_to_pci_reg mb_en_rd_mb_to_pci_reg Address Translator mb_add_in<31..0> mb_add_out<31..0> fifoemptyin pci_add_in<31..0> pci_add_out<31..0>

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