Progettazione di circuiti e sistemi VLSI

1. Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 10 3.5.2011 Temporizzazioni e sincronizzazione Temporizzazioni e sincronismo

2. Synchronous Timing tc-q tp,comb tc-q,cd tcdlog tsu, thold Temporizzazioni e sincronismo

3. Latch Parameters D Q Clk T Clk PWm tsu D thold td-q tc-q Q Delays can be different for rising and falling data transitions tc-q + tp,comb + tsu≤ T tc-q,cd + tcdlog > thold Temporizzazioni e sincronismo

4. Register Parameters D Q Clk T Clk thold D tsu tc-q Q Delays can be different for rising and falling data transitions Temporizzazioni e sincronismo

5. Clock Uncertainties Sources of clock uncertainty Temporizzazioni e sincronismo

6. Clock Nonidealities • Clock skew • Spatial variation in temporally equivalent clock edges; deterministic + random, tSK • Clock jitter • Temporal variations in consecutive edges of the clock signal; modulation + random noise • Cycle-to-cycle (short-term) tJS • Long term tJL • Variation of the pulse width • Important for level sensitive clocking Temporizzazioni e sincronismo

7. Clock Skew and Jitter Clk tSK Clk tJS • Both skew and jitter affect the effective cycle time • Only skew affects the race margin Temporizzazioni e sincronismo

8. Clock Skew # of registers Earliest occurrenceof Clk edge Nominal – /2 Latest occurrenceof Clk edge Nominal + /2 Clk delay Insertion delay Max Clk skew  Temporizzazioni e sincronismo

9. Positive and Negative Skew Temporizzazioni e sincronismo

10. Positive Skew Launching edge arrives before the receiving edge Temporizzazioni e sincronismo

11. Negative Skew Receiving edge arrives before the launching edge Temporizzazioni e sincronismo

12. Timing Constraints Minimum cycle time: T -  = tc-q + tsu + tlogic Worst case is when receiving edge arrives early (positive  negative skew) Temporizzazioni e sincronismo

13. Timing Constraints Hold time constraint: t(c-q, cd) + t(logic, cd) > thold +  Worst case is when receiving edge arrives lateRace between data and clock Temporizzazioni e sincronismo

14. Impact of Jitter Temporizzazioni e sincronismo

15. Longest Logic Path in Edge-Triggered Systems tJI + d tSU Clk tClk-Q TLM T Latest point of launching Earliest arrivalof next cycle Temporizzazioni e sincronismo

16. Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: tc-q + TLm,cd + tSU < T – tJI,1 – tJI,2 - d Minimum cycle time is determined by the maximum delays through the logic tc-q + TLm,cd + tSU + d + 2 tJI < T Skew can be either positive or negative Temporizzazioni e sincronismo

17. Shortest Path Earliest point of launching Clk tClk-Q TLm,cd Clk tH Data must not arrivebefore this time Nominalclock edge Temporizzazioni e sincronismo

18. Clock Constraints in Edge-Triggered Systems If launching edge is early and receiving edge is late: tc-q,cd + TLm,cd – tJI,1 < tH + tJI,2 + d Minimum logic delay tc-q,cd+ TLm,cd < tH + 2tJI+ d Temporizzazioni e sincronismo

19. How to counter Clock Skew? Temporizzazioni e sincronismo

20. Latch-Based Design L1 latch is transparentwhen f = 0 L2 latch is transparent when f = 1 f L1 L2 Logic Latch Latch Logic Temporizzazioni e sincronismo

21. Clock Distribution H-tree Clock is distributed in a tree-like fashion Temporizzazioni e sincronismo

22. The Grid System • No rc-matching • Large power Temporizzazioni e sincronismo

23. Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol Temporizzazioni e sincronismo

24. Synchronous Pipelined Datapath Temporizzazioni e sincronismo