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PowerBench Programmable Power Supply Final presentation – part B March 22 th , 2009

HS DSL. PowerBench Programmable Power Supply Final presentation – part B March 22 th , 2009. Gregory Kaplan Dmitry Babin Supervisor: Boaz Mizrahi. Topics. Overview Basic reminder Targets and expectations Top-level survey of the implementation Implementation Schematics CAD simulations

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PowerBench Programmable Power Supply Final presentation – part B March 22 th , 2009

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  1. HS DSL PowerBench Programmable Power SupplyFinal presentation – part B March 22th, 2009 Gregory Kaplan Dmitry Babin Supervisor: Boaz Mizrahi

  2. Topics • Overview • Basic reminder • Targets and expectations • Top-level survey of the implementation • Implementation • Schematics • CAD simulations • Layout • Design guidelines and overview • Features of interest • Mechanics • Thermal • UI • Future developments

  3. OverviewA brief reminder Overview A brief reminder User interface D U T Power supply Control unit Measurement unit Active load User interface for standalone operation LEDs LCD Keys

  4. Power supply unit capabilities Variable source/sink operation Four independent outputs Configurable current limits Fast load transient simulation DRAM-like power consumption simulation Two-way communication with a PC Overview Design targets vs projected capabilities I       OverviewDesign targets vs projected capabilities I

  5. Overview Design targets vs projected capabilities II         OverviewDesign targets vs projected capabilities II • Source operation • Output voltage: 0.9 to 12.6 V • Output current: 0 to 3.5 A • Programming resolution: < 5 mV • Ripple and noise: < 20 mV peak-to-peak • Settling time: < 1 ms • Load operation • Input current: 0 to 3.5 A • Programming resolution: < 1 mA • Fast (< 100 ns) transient load simulation

  6. OverviewControl Scheme Overview Control Scheme DAC Output setting DC-DC Converter Post regulator Current Sense Controller Block Input voltage sense feed- forward PWM Output AuxiliaryVoltage Sense ADC Tempe-rature Current limit ADC Voltage Sense ADC Microprocessor FPGA

  7. OverviewSource/Sink/Measurement Module 1 (Outputs 1, 2 Overview Source/Sink/Measurement Module 1 (Outputs 1, 2) 1 SOURCE/SINC 14 ADC DATA 2 ADC CONTROL 1 CLR AD5415YRUZ 4 SPI D/A Converter 4 SPI 14 ADC DATA 2 ADC CONTROL VDD 1 SOURCE/SINC VDD MOSFET Driver MIC4102YM OUTPUT 1 2 PWM RETURN 1 LT2296- CUP TO/FROM FPGA AD79144-Ch 10-bit ADC A/D Converter LT2296- CUP MIC4102YM OUTPUT 2 2 PWM RETURN 2 MOSFET Driver

  8. OverviewSource/Sink/Measurement Module 2 (Outputs 3, 4) Overview Source/Sink/Measurement Module 2 (Outputs 3, 4) VDD MOSFET Driver MIC4102YM OUTPUT 3 2 PWM RETURN 3 1 SOURCE/SINC 14 ADC DATA LT2296- CUP 2 ADC CONTROL TO/FROM FPGA 1 CLR AD5415YRUZ AD79144-Ch 10-bit ADC A/D Converter 4 SPI D/A Converter LT2296- CUP 4 SPI 14 ADC DATA 2 ADC CONTROL VDD VDD 1 SOURCE/SINC FAN3227TMX OUTPUT 4 2 PWM RETURN 4 MOSFET Driver

  9. OverviewControl Module Overview Control Module CY7C68013A -100AXC High-Speed USB USB USB Control 5 USB CONTROL 16 DATA 4 I2C 2 1 RTC-8564JE 5 8 4 1 LM75 CIM-5 Real Time Clock Graphic LCD Module Optrex F-51553GNBJ -LW-AEN Temperature monitor (2 devices) Keypad PB0 PB1-PB4 M25P20 -VMN6 2Mbit SPI Flash SPI DATA IN, OUT, CLK 3 SPI CS,WP,HOLD Xilinx SPARTAN 3-E XC3S250E-4-PQ208 16 DATA SPI Microchip PIC18F87J50 -I/CT USB CONTROL TO/FROM SSM MODULE DAC 2 USB Port 2 PROG_B*,DONE* PWM ADC Output ADC Control * Dedicated conf pins

  10. OverviewPower flow – Control Module Overview Power flow – Control Module 2.5V 1.2V VDD Vcore VDD VDD VDD VDD Vaux Microchip PIC18F87J50 M25P20 CY7C68013A RTC-8564JE Xilinx SPARTAN 3-E Up to 222mA Up to 15mA Up to 85mA Up to 0.8mA More than 100mA Graphic LCD Module Optrex F-51553GNBJ -LW-AEN VDD Up to 42mA AC/DC Converter ECM100 15.8V 5V, VBAT+0.3V or VBAT LM3668SD 3.3V Buck-Boost Universal Input Up to 100W LTC4090 TPS73001 2.5V LDO Li-ion 3.7-4.2V (optional) DC/DC Converter + Battery Charger TPS62003 1.2VBuck 3.3V BR1255 Small Li battery (optional) DC/DC Booster FAN4855MTC 5V 5V, VBAT+0.3V or VBAT

  11. OverviewPower flow - Source/Sink/Measurement Module Overview Power flow - Source/Sink/Measurement Module Boost ADP1611 15.8V (From AC or battery) 3.3V 5V, VBAT+0.3V or VBAT Inverter LT3580 -15.8V (From AC or battery) AC/DC Converter 15.8V (Direct from AC) ECM100 Universal Input Up to 100W DAC 14 bit ADC DAC 14 bit ADC DAC 10 bit ADC 14 bit ADC DAC 14 bit ADC MOSFET Driver OUTPUT 1 RETURN 1 ×4

  12. Topics • Overview • Basic reminder • Targets and expectations • Top-level survey of the implementation • Implementation • Schematics • CAD simulations • Layout • Design guidelines and overview • Features of interest • Mechanics • Thermal • UI • Future developments

  13. Implementation • 3 separate boards from the start: • “Digital” – control board • “Analog” – sink/source/measurement (SSM) • “Panel” – user interface (UI) • The design process: • Component selection • Schematics • Simulation • Layout

  14. Implementation – Schematics Introduction • Environment: • OrCAD Capture 16.0 • Custom library for all the parts • Hierarchical design • Use of “instances” where applicable • Component selection • Priority to Zoran stock when possible • Minimum different components • All ICs in “accessible” packages (no DFN or BGA except when unavoidable) • Price • Design guidelines • Clear schematics with maximum relevant information • Maximum flexibility in the post-layout stage • Scalability and “overheads”

  15. Implementation – Schematics Control Module : Clock • Clock buffer and oscillator running at 24MHz • Alternate clock sources (crystals) can be used for the MCU and USB chips

  16. Implementation – Schematics Control Module : Power distribution I • A dedicated power manager IC select from either high-voltage DC line, battery or USB power sources, converting them to a voltage around the battery voltage or 5V • It also charges the battery when possible (and permission is granted by the MCU)

  17. Implementation – Schematics Control Module : Power distribution II • The 3.3V converter masters other secondary converters (the 5V, 2.5V and 1.2V ones): • while 3.3V rail is low, all secondary converters are turned off (including the 3.3V converter itself!) • while 3.3V rail is high, secondary converters may be turned on/off by the MCU (if 3.3V is turned off, the system may be turned on only by a button)

  18. Implementation – Schematics Control Module : Connectors • Connection to the other boards • 120-pin 0.1” connector to the SSM module • 40-pin 0.1” connector to the UI module • End-user interface • USB-B connector • Debug and programming • JTAG • ICSP • 12-pin and 14-pin debug ports on the USB chip • 2 x 38-pin MICTOR connectors • 2 SMA-type connector footprints

  19. Implementation – Schematics Control Module : Connectors • The SSM module connector • Signal speed of up to 100MHz • Adequate grounding around clock lines • No crossing between signals (will be shown later in the layout stage) • “Fast” lines spread between “slow” lines

  20. Implementation – Schematics SSM Module : DC-DC Buck Converter • A buck DC-DC converter • Input: 15.8V • Output: 0..X V • Maximum operating frequency: Y KHz • Estimated efficiency: Z% • Can work both in continuous and discontinuous conduction modes • High-frequency spikes are rejected by the output ferrites

  21. Implementation – Schematics SSM Module : Positive LDO • A low-dropout post-regulator • Input: X ..Y V • Output: 0..X V • Loop bandwidth: X MHz • Actively controlled by the DAC output • Proposed mode of operation: constant power dissipation • Smoothes the buck converter’s output ripple

  22. Implementation – Schematics SSM Module : Active load • A varying load • Resistance varies from X Ohm to Y Ohm • Loop bandwidth X MHz • Desired current is set by the output of the DAC • Too much output inductance can interfere with operation

  23. Implementation – Schematics SSM Module : Mode switching • A low-resistance circuit used to switch between the source and sink modes • Resistance X mOhm • Switching time Y msec

  24. Implementation – Schematics SSM Module : Current sensing A fully differential instrumentation amplifier reads the voltage across a 30mOhm resistor in the power path, amplifying it by X times before feeding a differential pair to the ADC. Amplifier bandwidth is 1 MHz.

  25. Implementation – Schematics SSM Module : Power distribution example Generation of the -15.8V supply rail from battery or the +15.8 DC input and its distribution to the different channels

  26. Implementation – Schematics SSM Module : DC-DC Cuk Converter A converter that inverts the +15.8V power input to generate a 0..-12.6V output:

  27. Implementation – Schematics SSM Module : 4-Ch 10-bit ADC Measuring the outputs of the DC-DC converters before the post-regulator in each of the 4 channels

  28. Implementation – Simulations Introduction • Environment: • PSPICE • LTSPICE • Texas Instruments simulator • Simulation goals: • Switching times • Stability (open + closed loop) • Voltage levels • Reliability • Key simulations: • Power ORing circuits • All amplifier circuits (LDO, active load, active filters) • All analog switches • Major obstacles • Highly non-linear circuits • Unknown external load parameters

  29. Implementation – Simulation Active load – open loop response Green: Open loop gain (dB) Red: Open loop phase (deg) • Below is shown a PSPICE simulation of the open loop response of the active load circuit: • Load current: 200mA • DUT voltage: 12.6V • 0-dB point – 4Mhz • Phase margin: 71.4deg • Gain margin : 25.5dB

  30. Implementation – Simulation Active load – transient behavior Green: Control input voltage Red: DUT current • Below is shown a PSPICE simulation of the transient behavior of the active load circuit: • Load current step: 1A with a rise/fall time of 500ns (2MHz) • DUT voltage: 12.6V • Overshoot: 95mA • Settling time: 300ns to within 5% • Assumed lead inductance of 0.5uH and contact resistance of 150mOhm

  31. Implementation – SimulationInstrumentation amplifier – frequency response Green: Control input voltage Red: DUT current • Below is shown a PSPICE simulation of the frequency response of the instrumentation amplifier used as the active filter in the current sense circuit: • Bandwidth: 1MHz • Maximum ripple within bandwidth: 0.4dB • DC gain: 19.5dB

  32. Implementation – SimulationMode switch circuit - transient • Below is shown a PSPICE simulation of the frequency response of the switching circuit used to select between the source and sink functions • Switching time: • Maximum resistance:

  33. Implementation – Debug • Control module: • ICSP port • JTAG port • 2 MICTOR connectors in parallel to most major data and control lines • 2 free Cypress ports available for debugging (test points) • 4 DIP switches and 4 LEDs on dedicated debug IOs of FPGA • Ground test points spread across the board • SSM module • Ground test points spread across the board • Most components in packages with leads to enable easy connection

  34. Topics • Overview • Basic reminder • Targets and expectations • Top-level survey of the implementation • Implementation • Schematics • CAD simulations • Layout • Design guidelines and overview • Features of interest • Mechanics • Thermal • UI • Future developments

  35. Layout Introduction • Environment • OrCAD 16.0 netlists • Mentor PCB Layout tools • Design Guidelines • Signal reliability (minimize crosstalk and parasitics) • EM compatibility (low emissions and susceptibility) • Thermal considerations • Mechanical considerations

  36. Layout Control Module - Overview Connection to SSM module Connection to UI module and debug interfaces Debug Control hardware Power • 167x168 mm • 6 layers • 1 oz copper • Stackup: • Component side: signal • Ground • Signal + low power • Signal + low power • Power • Print side: signal • Components on both sides

  37. Layout SSM Module - Overview

  38. Layout SSM Module – Signal path

  39. Layout SSM Module – Power path

  40. Layout SSM Module – Power planes

  41. Layout UI Module

  42. Layout SSM Module – Overview • 157x168 mm • 8 layers • 1 oz copper • Stackup • Component side: signal • Layer 2: power • Layer 3: signal (horizontal) • Layer 4: signal (vertical) • Layer 5: GND • Layer 6: differential striplines • Layer 7: GND • Print side: signal • Components on both sides

  43. Layout UI – Overview • 110x230 mm • 2 layers • 1 oz copper • Stackup • Component side: signal + power • Print side: signal + power • Components on both sides

  44. Topics • Overview • Basic reminder • Targets and expectations • Top-level survey of the implementation • Implementation • Schematics • CAD simulations • Layout • Design guidelines and overview • Features of interest • Mechanics • Thermal • UI • Future developments

  45. Mechanical Design Introduction • 3 boards – one system case • Hard plastic (ABS) case: 260x180x105 mm • Battery and power supply included • Cutouts: user interface and connectors (power, USB) • Environment • Google SketchUp 6.0

  46. Mechanical Design User Interface • Graphic 128x64 LCD (up to 8x16 text characters) • 4x4 Keypad + ‘Enter’ key • 4 ‘soft’ keys under the LCD • 4 LED indicators • Power on / battery on indicator • Buzzer

  47. Mechanical Design Thermal characteristics • Characteristics: • When sinking current, each channel can generate up to 25W of heat • When sourcing current, losses of up to 3W per channel are expected • Self-power circuits exhibit efficiencies of around 90%, meaning thermal losses on the order of up to several watts overall • Solutions: • Ventilation holes throughout the case • All heat-generating components chosen so that they can withstand the temperature rise • Big custom-made heatsink attached to the transistors of the source/sink stages • External fans will be added to the case • Constant temperature monitoring by the MCU enable shutdown in case of overheating

  48. Statistics 1 project 2 partners 3 boards 10 months ~60 breakfasts at Zoran 129 different electronic components ~1700 man-hours 996 nets 1221 total electronic components 4017 solder pads 609 710 399 bytes in project folder

  49. From now on: Looking for code monkeys

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