1 / 22

DBBC - A Flexible Platform for VLBI Data Process

4th General Meeting International VLBI Service January 9-13, 2006 Universidad de Conception NEXT GENERATION VLBI2010. DBBC - A Flexible Platform for VLBI Data Process. G. Tuccari, S. Buttaccio, G. Nicotra - Istituto di Radioastronomia CNR - Italy

udell
Download Presentation

DBBC - A Flexible Platform for VLBI Data Process

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 4thGeneral Meeting International VLBI Service January 9-13, 2006 Universidad de Conception NEXT GENERATION VLBI2010 DBBC - A Flexible Platform for VLBI Data Process G. Tuccari, S. Buttaccio, G. Nicotra - Istituto di Radioastronomia CNR - Italy Y. Xiang - Shanghai Astronomical Observatory, CAS – China M. Wunderlich - Max Planck Institute fuer Radioastronomie, Bonn - Germany IVS-4th General Meeting, Concepción- Chile, Jan 2006

  2. DBBC Project • ‘DBBC’ is a project supported by the European VLBI Network for the development of a Digital Base Band Converter • The main goal was to replace the existing terminal with a complete compact system to be used with any VSI compliant recorder or data transport • Hardware programmability is the main feature in order to optimize the architecture to the needed performance having the possibility to arrange different architecture in the same hardware support • The new development is compatible with the existing terminals and correlators IVS-4th General Meeting, Concepción- Chile, Jan 2006

  3. DBBC Project (cont.) • The new backend is fully up-gradable and ready to process larger bandwidth with new generation correlators • Upgrade or improvements is mostly only software • Upgrade is also possible in hardware replacing compatible ‘pin-to-pin’ processing modules • Data out as VSI interfaces IVS-4th General Meeting, Concepción- Chile, Jan 2006

  4. DBBCGeneral Features • 4 RF/IF Input from 16 in the range 0.001-2.200 GHz • Four polarizations or bands available for a single group of 64 output data channel selection (support 2 VSI) • 230,29 Hz frequency sampling clock • Channel bandwidth ranging between 250KHz and 16 MHz (MK4) • Channel bandwidth between 32 and 512 MHz (wide modes) • Tuning step 1 Hz • Multiple architecture using fully re-configurable FPGA Core Modules (Down-Converter, Equally Spaced Multichannel, etc.) • Modular realization for cascaded stack processing IVS-4th General Meeting, Concepción- Chile, Jan 2006

  5. DBBC General Schematic PCI Interfaces PC FS PC IFC1,2,3,4 IFA1,2,3,4 IFB1,2,3,4 IFD1,2,3,4 AGC/ Filter AGC/ Filter AGC/ Filter AGC/ Filter F I L A ADB 1 ADB2 ADB 3 ADB 4 HSI HSIR HSI HSIR HSI HSIR F I L A 2xVSI 64 ch CORE CORE CORE 230,29 MHz Synthesizer HSO HSO HSOR HSO HSOR HSO HSOR Analog Monitor CCM CCM CCMR CCM CCMR CCM CCMR H-Maser IVS-4th General Meeting, Concepción- Chile, Jan 2006

  6. System Components • ConditioningModule • FiLa board – First/Last (VSI int., DA monit, Clock and Timing - 230,29 Hz Synthesizer, Communication, JTAG channel) • ADBoard – Analog to digital conversion • CoreModule boards – processing unit • FPGAs Core Firmware Configurations • PowerDistributor • PC Board + PCI interfaces (commercial) • System Management Software, Field System oriented IVS-4th General Meeting, Concepción- Chile, Jan 2006

  7. Schematic System Top View8U x 84 TE x 500 mm ConditioningModule min 1 – max 4 IF1 IF3 IF4 IF2 Ethernet ConditioningModule PC and Interfaces D I S K FiLa JTAG Adapter FiLa IF3 IF4 IF2 IF1 PowerDistributor 1 PPS 10 MHz VSI Monitor FiLaVSI ADB CoreModule FiLaVSI IVS-4th General Meeting, Concepción- Chile, Jan 2006

  8. ConditioningModule Pre-AD Conversion Signal Conditioning Pre-AD Conversion Nyquist Band Definition 4 IFs input selection Output Power Level Control Total Power Measurement IVS-4th General Meeting, Concepción- Chile, Jan 2006

  9. FiLaBoard First and Last board in the stack First: Communication Interface JTAG programming channel 1PPS synchronizer 229-30 Hz synthesizer Last: 2 VSI Interfaces DA Converter IVS-4th General Meeting, Concepción- Chile, Jan 2006

  10. ADBoard Analog to Digital Converter Analog input: 0 - 2.2 GHz Sampling clock: 230-29Hz Output Data: 2 x 8-bit @ 229-28 HzDDR IVS-4th General Meeting, Concepción- Chile, Jan 2006

  11. CoreModule Basic processing unit Max Input Rate: 4 x 8.589 Gb/s Max Output Rate: 8.192 Gb/s (64 ch @ 128 MHz) Programmable architecture Digital Down Converter: 1 CoreModule = 1 BBC Equally Spaced Multichannel: 1 CoreModule = 64 channels IVS-4th General Meeting, Concepción- Chile, Jan 2006

  12. Core Module Board • HIS/HSIR Cascade-able Input Bus 4x2x8-bit @ 229 MHz DDR • HSO Shared Output bus 2x32bit @32, 64, 128MHz • CCM Control / Configuration bus 32bit • CCM Monitor bus to DA converter 12 bit @500 MHz • 1 FPGA VirII-1152pin, 3000 (4000 - 6000 – 8000 compatible) • Stack cascade method to join up to 16 boards IVS-4th General Meeting, Concepción- Chile, Jan 2006

  13. DBBC4 ADBoard + 8 CoreModule Stack IVS-4th General Meeting, Concepción- Chile, Jan 2006

  14. Digital Base Band Converter IVS-4th General Meeting, Concepción- Chile, Jan 2006

  15. Digital Base Band Converter IVS-4th General Meeting, Concepción- Chile, Jan 2006

  16. PC Board: System Management Software • Standard commercial PC board including HD • Configuration files for each FPGA stored on HD • Software interface for FPGA configuration • Software interface for servicing FPGAs (I/O registers access) • Software interface for AD level control • Field System – like commands in standalone and remote (ethernet) IVS-4th General Meeting, Concepción- Chile, Jan 2006

  17. Minimal Architecture With fixed configuration and external RF control and clock generation: • 1 ADBoard • 1 CoreModule (multichannel configuration, or any other) • 1 FiLa board (VSI interface, DA converter, etc) • Components cost < 3.5 K€ IVS-4th General Meeting, Concepción- Chile, Jan 2006

  18. Maximum Architecture With fixed configuration and external RF control and clock generation: • 4 Conditioning Modules • 1 FiLa board • 4 ADBoard • 16 CoreModule • 1 FiLa board • PC and PCI interfaces IVS-4th General Meeting, Concepción- Chile, Jan 2006

  19. DBBC System in January 1st 2006 • Ready for testing in radiotelescopes • Next TOG in Westerbork in March demonstration on field • Program with observations/optimization • Update program for improving performance: - FPGA Virtex4 device for double processing clock and price reduction - Faster AD sampler for input bandwidth increasing - AD sampler placed inside the receiver and sampled data sent through an optical fiber - RFI Mitigation Board: the first CoreModule (same hardware) acts as RFI processor in transfer the pure sampled data with proper configuration. IVS-4th General Meeting, Concepción- Chile, Jan 2006

  20. First Results with the mDBBC prototype(collaboration Italy-China) • First digital x analog fringes detected on Nov 23, 2004 in the Seshan-Urumuqi baseline • First digital x digital fringes detected on Feb 2, 2005 in the Noto-Seshan baseline IVS-4th General Meeting, Concepción- Chile, Jan 2006

  21. Conclusions • The DBBC system is an high flexible instrument because is able to produce independent tunable channels for a full compatibility with the existing acquisition system and correlators. One CoreModule board is replacing a BBC module. • Combination of up to 4/16 IFs in a single module is possible. • The DBBC system is able to handle also equi-spaced multichannel configuration for producing contiguous not tunable channels. One CoreModule board is able to produce multiple channels. • More solutions are possible within the same system with software selection IVS-4th General Meeting, Concepción- Chile, Jan 2006

  22. The DBBC is here: Please ask if you need to have a look inside! IVS-4th General Meeting, Concepción- Chile, Jan 2006

More Related