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EVN dBBC

EVN dBBC. from G. Tuccari Istituto di Radioastronomia INAF. DBBC General Features • Four IFs Input in the range 10-512 or 512-1024 MHz • Four Ifs bands available for a single group of output data channel selection • 1.024 GHz fixed frequency sampling clock

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EVN dBBC

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  1. EVN dBBC from G. Tuccari Istituto di Radioastronomia INAF

  2. DBBC General Features • Four IFs Input in the range 10-512 or 512-1024 MHz • Four Ifs bands available for a single group of output data channel selection • 1.024 GHz fixed frequency sampling clock • Channel bandwidth ranging between 500KHz to 16 MHz (prel.) • Tuning step 50 KHz (prel.) • Multiple architecture using fully re-configurable FPGA Core Modules • Modular realization for cascaded processing • Field System support

  3. DBBC General Features (cont.) • Data out as single or double VSI interface • Total power measurement capability • Continuous Tsys measurement capability • Autocorrelation function for improving band shape • Pseudo noise and notes injection • Digital to analog converter monitor output • Digital AGC • Optional gigabit data transfer

  4. DBBC Status • • Prototype demonstrated at 32 MHz channel BW (on one end of baseline) • Single-channel dBBC boards being upgraded (newer Xilinx) to support four dBBC channels per board • Updated prototype expected complete end 2007 • VSI↔10GigE conversion board under development • Expected cost ~40KEuros for 16-channel system • Recent dBBC CDR gave go-ahead for continued development • Being jointly developed by CNR/MPI

  5. DBBC General Schematic View IFn (MHz) 1~512, 512~1024, 1024~1536, 1536~2048 IF 1 IF 2 IF 3 IF 4 AGC/ Filter AGC/ Filter AGC/ Filter AGC/ Filter A/D 1 A/D 2 A/D 1 A/D 2 HSI HSIR HSI HSIR HSI HSIR MK4/VSI max 64 ch CORE CORE CORE H-Maser Synthesizer / Distributor HSO HSOR HSO HSOR HSO HSOR VSI Interface FS PC PCI PC PCI Interfaces D/A Monitor The first CoreBoard is performing RFI active mitigation

  6. MK4/VLBA-like Schematic Top View ConditioningModule min 1 – max 4 IF1 IF3 IF4 IF2 Ethernet ConditioningModule PC and Interfaces D I S K FiLa JTAG Adapter FiLa IF3 IF4 IF2 IF1 PowerDistributor 10 MHz CaT 1 PPS VSI Monitor CoreBoard min 1 – max 16 FiLa ADBoard min 1- max 4 FiLa

  7. 4 ADBoard + 8 CoreModule Stack

  8. DBBC – Backend

  9. The End

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