Chip design < Work on pALPIDEfs >

Chip design < Work on pALPIDEfs > KIM,D.H. , KWON,Y. ,SONG,M.K. Department of Semiconductor Science, DonggukUniv. for the ALICE collaboration. Department of Physics, Yonsei Univ. for the ALICE collaboration.

< CONTENTS > • pALPIDEfs– work on DACs • pALPIDEfs version 2 – work on I/O PAD • Next plan

I. pALPIDEfs – work on DAC - Layout of pALPIDEfs Pixel Matrix: sensitive area Matrix DACs Periphery Logic I/O pads Periphery circuit ( DACs, PADs, periphery readout logic, etc)

I. pALPIDEfs – work on DAC DAC - List of Voltage and Current DACs

VREF I. pALPIDEfs – work on DAC DAC – Voltage DAC • Block diagram & Simulation result AVSS <Voltage DAC resistor divider> <Voltage DAC unit block > <Voltage DACS output range at nominal corner simulation>

I. pALPIDEfs – work on DAC DAC – Current DAC • Block diagram & Simulation result • <Current DACs, corner simulations results> <Current DACs scheme>

II. pALPIDEfs Version 2 – work on PAD - Specification of I/O PAD 10 Ω 50 Ω 10 Ω 50 Ω 40kΩ 40kΩ Pull down or Pull up Pull down or Pull up DVDD or DVSS DVDD or DVSS 6pF 6pF 100um 21cm • Total Load at the output driver • RLOAD = 3.57Ω + 10 Ω≈ 14Ω • CLOAD = 6pF x 7 + 21pF ≈ 65pF • Property of Cable • R=170mΩ/cm @ W= 100um • C=1pF/cm @ W= 100um 3.57 Ω 21pF • RCABLE = 3.57 Ω • CCABLE = 21pF

II. pALPIDEfs Version 2 – work on PAD - design of I/O PAD OEN D_OUT PAD CIN OEN D_OUT PAD CIN CIN DOUT DVSS Buffer & Resistor 92um DVDD ESD diode AVSS AVDD 90um < Block diagram of I/O PAD> SUB < Layout of I/O PAD>

II. pALPIDEfs Version 2 – work on PAD - Simulation result of I/O PAD Dout • Post simulation result of PAD_I/O (with parasitic parameter) • Output driver : Delay < 5ns @ Load : 4Ω, 65pF • Input buffer : Load : 0.5Ω, 160fF OEN D_OUT PAD CIN

III. Next plan - Study of discriminator • Analysis of front-end and design new structure OEN D_OUT PAD CIN <pALPIDEfs Front-End principle>

Thank you

Chip design < Work on pALPIDEfs >