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The Creation of a New Computer Chip. The Concept. A group of people from marketing, design, applications, manufacturing and finance develop the basic concept, features and rough specifications for a new product. They all go off and work on their particular pieces of the proposal.
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The Concept A group of people from marketing, design, applications, manufacturing and finance develop the basic concept, features and rough specifications for a new product.
They all go off and work on their particular pieces of the proposal Marketing – what are the customers asking for and what will sell vs. the competition, what is the marketing plan, what will it cost Design – how will it be designed, how long will it take, what design tools will be necessary, how many people will it take, what will it cost Manufacturing – how will it be manufactured, what tooling will be necessary, how many manufacturing lines will it need, what will it cost Finance – will the product make money, what is the return on investment, what resources are available and what will need to be acquired, what will it cost
The Decision They all get back together again with management and decide whether or not to proceed will the project.
GO! Once the decision is made to proceed, the design team swings into action
The Design Flow Block Level RTL Level RTL Simulation Logic Level Logic Simulation Transistor Level Extract Parasitics & create timing model Physical Layout Level – (masks)
Registers ALU Memory Clock & Timing Control The Block Diagram The problem is broken down into basic functions blocks and the interfaces are specified Branch Control I/O
The High Level Description The blocks are then broken down into functional units and registers. The functionality is coded in a high level descriptive language. This is known as the RTL description. Register File IR operand selection and register control master control ALU control ALU
The High Level Simulation The RTL description is simulated to ensure that the design performs as it should.
The Logic Level Description The functional units are then broken down into logic gates and registers. This is known as the logic level description.
The Logic Level Simulation The logic description is simulated to ensure that the design performs as it should. It is also compared against the RTL simulation.
P The Transistor Description The logic gates are broken down to their component transistors. From this description, the timing delays and electrical parasitics can be estimated. If necessary, transistors can be resized. OR N type P type Field Effect Transistors
S S G G D D Field Effect Transistor Operation P type N type Gate = Ground = ‘0’
S S G G D D Field Effect Transistor Operation P type N type Gate = Vcc = ‘1’
N Type Field Effect Transistor no current flow GND P type substrate Silicon Wafer GND
N Type Field Effect Transistor Vcc P type substrate Silicon Wafer GND
N Type Field Effect Transistor Vcc P type substrate Silicon Wafer GND
N Type Field Effect Transistor current flow Vcc P type substrate Silicon Wafer GND
P Type Field Effect Transistor no current flow Vcc Vcc N-Well P type substrate Silicon Wafer GND
P Type Field Effect Transistor GND Vcc N-Well P type substrate Silicon Wafer GND
P Type Field Effect Transistor GND Vcc N-Well P type substrate Silicon Wafer GND
P Type Field Effect Transistor current flow GND Vcc N-Well P type substrate Silicon Wafer GND
I1 I O I O O I2 I1 O I2 I2 P P P P P O O I1 I1 I2 Logic Gate Implementation Using Field Effect Transistors
So how do we build Field Effect Transistors? We start with a blank piece of silicon wafer P type substrate P type substrate Silicon Wafer Silicon Wafer
Cover it with an N-well Mask P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Bombard it with negatively charged ions to create the N-well N type dopant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Create the N-well N type dopant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Create the N-well N type dopant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Grow the Gate Oxide layer P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Grow the Gate Oxide layer P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Deposit Polysilicon P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Cover it with a Polysilicon mask P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Etch the Polysilicon and Oxide Etchant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Etch the Polysilicon and Oxide Etchant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Etch the Polysilicon and Oxide Etchant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Etch the Polysilicon and Oxide P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Cover it with an N Transistor mask P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Implant the N type Dopant N type dopant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Implant N Dopant N type dopant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Cover it with a P Transistor mask P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Implant P Dopant P type dopant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Implant P Dopant P type dopant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Grow more Oxide P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Grow more Oxide P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Cover it with a Contact mask P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Etch the Oxide Etchant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Etch the Oxide Etchant P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Deposit Metal P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Deposit Metal P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer
Cover it with a Metal mask P type substrate P type substrate P type substrate P type substrate Silicon Wafer Silicon Wafer Silicon Wafer Silicon Wafer