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FERMAT | Sandeep Shukla | June 2005 {shukla}@vt.edu. ESL: Panacea or Hype?. Acknowledgement: NSF, Project Espresso @IRISA, FERMAT @Virginia Tech, and the “Chip Design” Magazine. Outline. Pictures speak louder than words What is ESL? Abstraction Trends Verification Trends
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FERMAT | Sandeep Shukla | June 2005 {shukla}@vt.edu ESL: Panacea or Hype? Acknowledgement: NSF, Project Espresso @IRISA, FERMAT @Virginia Tech, and the “Chip Design” Magazine IRISATECH DAY
Outline • Pictures speak louder than words • What is ESL? • Abstraction Trends • Verification Trends • EDA Industry Trends • What are we doing? • Heterogeneity and MoCs • Behavioral Hierarchy • Meta Modeling Support • Service Oriented Validation Framework IRISATECH DAY
Hardware Resources and Computer Power IRISATECH DAY
HW/SW Cost Breakdown Trends IRISATECH DAY
Abstraction Trends IRISATECH DAY
Hybrid and AMS IRISATECH DAY
Electronic System Level? IRISATECH DAY
Verification Trends IRISATECH DAY
Verification Gap IRISATECH DAY
Verification Trends IRISATECH DAY
A Tale of Two ESLs? IRISATECH DAY
ESL Industry Space IRISATECH DAY
Our Work at FERMAT and ESPRESSO • Introduce Heterogeneity in SystemC with Models of Computation (MoC) extensions • Raise the Modeling Fidelity • Step towards Behavioral Hierarchy with Heterogeneity • EWD: Meta-Modeling Frameworks • CARH: Service Oriented Validation Framework IRISATECH DAY
SystemC’s Discrete-Event Kernel • Evaluate-Update Paradigm • Dynamic scheduling incurs unnecessary delta cycles • Statically schedulable MoCs should avoid dynamic scheduling IRISATECH DAY
An Example MoC Extension: Synchronous Data Flow in SystemC • SDF models are: • Amenable to static scheduling • Require blocks to have predefined production and consumption rates • Construct repetition vector • Construct firing order • Executable schedule achieved with valid repetition vector and firing order IRISATECH DAY
An Example MoC Extension: Synchronous Data Flow in SystemC SC_MODULE( sdf_block ) { SDFPort< sc_uint< 8 > > sample_in; SDFPort< sc_uint< 8 > > sample_out; SC_SDF_METHOD( block_entry ); SC_CTOR( sdf_block ) { // Register this block into sdf_graph } void block_entry() { // Entry specific code } }; SC_MODULE( toplevel ) { sc_in_clk CLK; SC_THREAD( topentry ) { sensitive << CLK.pos(); }; SC_CTOR ( toplevel ) { // Instantiate SDF blocks and connect // the ports } void topentry() { sdf_trigger(); } }; • Constructing an SDF model requires: • Encapsulating SDF specific processes (SC_SDF_METHOD) in a top-level SystemC process • Top-level constructs SDF graph with appropriate API • Every unique SDF model must be registered in its own sdf_graph instance • Top-level entry function must invoke sdf_trigger() function IRISATECH DAY
An Example MoC Extension: Synchronous Data Flow in SystemC • During initialization all executable schedules are computed • DE kernel continues executes without intervention until sdf_trigger() is invoked • SDF kernel takes over and executes the SDF-specific blocks according to the computed schedule IRISATECH DAY
Heterogeneous ExtensionsCommunicating Sequential Processes Fork2 • Rendez-vous communication Fork1 Phil3 Phil2 Fork3 Footman Phil4 Phil1 Fork0 Phil0 Fork4 IRISATECH DAY
s0 s1 s2 s3 s4 Heterogeneous ExtensionsFinite State Machine Fork2 • Control machines Fork1 Phil3 Phil2 Fork3 Footman Phil4 Phil1 Fork0 Phil0 Fork4 IRISATECH DAY
SDF: Producer/Consumer Producer Consumer Heterogeneous ExtensionsDE, FSM, SDF & CSP Fork2 DE: Solves RSA Encryption Algorithm Fork1 Phil3 Phil2 Fork3 SDF: Sobel Edge Detection Algorithm Footman Phil4 Phil1 Fork0 Phil0 Fork4 IRISATECH DAY
Simulation EfficiencyA brief look • Pure SDF models ~ 65% gains • Pure FSM models ~ 10% degradation • Pure CSP models ~ 1% gains IRISATECH DAY
Behavioral Hierarchy with Heterogeneity • Decompose design into small behaviors • Behaviors expressed by different MoCs IRISATECH DAY
Behavioral Hierarchy with Heterogeneity • Semantics define interactions within MoC and across MoCs • Hierarchical composition IRISATECH DAY
Doxygen Annotated XML SystemCXML: http://systemcxml.sourceforge.net SystemC Source Phase 1 Extracted XML Phase 2 IR Analysis, Transformation, Testing, Optimization, … IRISATECH DAY
Service Oriented Validation • Service-oriented architecture • Provide infrastructure for incorporating multiple features into services using ACE/TAO • Use SCV for automated testbench generation • Dynamic-Value Change Dump • Logging Service • Employ existing CORBA services such as: • Naming Service • Event Service IRISATECH DAY
Meta-Modeling • Metamodeling framework • Creating metamodels • Meta model allows an abstract description • Facilitates modeling using metamodel abstract • syntax • Eg.: GME (Generic Modeling Environment) • GME • Abstract syntax using pure UML class diagrams • Semantic constraints using the Object Constraint • Language (OCL) • XML access for both model and metamodel • information IRISATECH DAY
Meta Modeling IRISATECH DAY
Features of EWD • A visual environment that supports heterogeneous modeling • Executable simulation models are automatically built by the tool and currently the target simulation languages are • SML and Haskell-based modeling extensions. • Translation to other targets such as SMV for formal verification purposes • Multi-targeting is achieved through XML-based interoperability IRISATECH DAY
Reference • Website for SystemC-H: http://fermat.ece.vt.edu/systemc-h/ • Book IRISATECH DAY