Stave Status and Plans

Stave Status and Plans Carl Haber 12-Aug-2008 UCSC

Prototypes and Designs 60 cm, 9 cm strip, 6 segments/side Stave-06 1 meter, 3 cm strip, 30 segments/side 192 Watts (ABCD chip), ~2.4 % Xo + support structure Stave-07 6 x 3 cm, 6 chips wide 1.2 meter, 2.5 cm strip, 48 segments/side ~250-300 Watts (@0.25 W/chip) 1.7 – 2.4 % Xo + support structure, depends upon coolant and hybrid design Stave-08 10 x 10 cm, 10 chips wide

Stave 2007 - Ongoing Program • At present 8 modules have been mounted on Stave-2007 • 30 hybrids have been mounted on test vehicle stave • Individual hybrids/modules work well electrically • Main issue has been data transmission on the stave with multiple modules. • Lack of robust response to LVDS commands although signals look OK – sometimes it all works, other times not… • Significant work on test bench with D.Nelson (many thanks for this…) • While we have made a number of improvements we are not there yet • This has delayed further mounting of modules on Stave-2007

Multidrop Distribution, Serial Power 30 modules serial power (ABCnext will be 30 V)

continued • We will continue to pursue the Stave-2007 program • Dave has built a new repeater board between NI and stave • Add diagnostics • Investigation of grounding in this serial system • Local grounds • SP ground • DAQ ground • HV ground(s) • Replace passive SMC with better impedance match • LVDS receiver component values and biasing • We certainly aim to complete Stave-2007 before NIKHEF but need to converge on data transmission aspect soon.

Stave 2008 Program • Timescale: Winter-Spring 2009 • Hybrids • DAQ • Substrates • Glue • Bus Cable • Mechanics and Materials

Hybrid for Stave-2008, ABC-next • AM presentation • Oxford Meeting July 30-31, 2008 • Liverpool to lead here • A key issue has been how to accommodate robust early testing of the ABC-next and Stave-2008, considering the lack of a MCC • Proposed HYBRID -1-2-3 program • Drive towards a minimum area design • Concern for data transmission problems • Parallel bus testing program • Hybrid 1-2-3 should occur over next 6-9 months

DAQ • Way back the need for a multi-module DAQ was recognized: Mustard not optimal • Identified NI-PXI-656X system as a candidate • System developed and in use. • Considerable software written • Shortcomings identified – speed, reliability? • Alternate proposals

New Stave Test DAQ • A bench top system configured for parallel testing large numbers of modules • Use off-the-shelf PXI based DAQ cards from National Instruments • PXI-656X 16 channels of LVDS I/O, multiple card system, 160 Mb/s system • on-board memory/channel 2,16, or 128 Mb But no hardware histogramming • Software “StaveDAQ” contains all the existing SCT tests • StaveDAQ is written in LabView, HSDIO library • Noise interference and external trigger tests included • Configurable framework to handle any combination of components, cards • Reporting, data access, and comparison tools • Measurements agree with MUSTARD/SCTDAQ system 10-20-30 module system

Response Curves on the Stave comparison S-curve threshold VT50 Output noise gain noise

Use with ABC-Next, Stave-2008 • The 6561 or others in this series can run at 200 MHz so should be compatible with ABC-next (this is why we started here as well) • How to use it with the ABC-next? • Command line would need to be programmed with new scripts • Devote one output to Level 1 • Clock options: have to understand whether we should run the system clock at 160 MHz to sync with data and divide it down on a support card to get the BCO clock • New functions to read registers • Software support issue – don’t have resources at LBNL now to support distribution of software, state BNL or others will do this if needed. • To be useful this is needed around the time ABC-Next arrives Oct-Nov

Alternatives • Both Cambridge (developed Mustard) and SLAC have proposed a standalone FPGA card for stave DAQ. • Card would parse data and histogram in hardware • Link to host by USB or Ethernet • This would be faster and (perhaps) cheaper • Require firmware development • Can this be embedded in some of the existing code: SCTDAQ (ROOT) or StaveDAQ (LV)? • Who would do this work?

continued • The SLAC propsal is based upon an existing platform (LCLS I/O Card) and uses the same Xilinx Virtex considered by Cambridge • Held a meeting at UC London on 8/1 to discuss this • CH, Phillips, Maurice Goodrick, Matt Warren • Contingent upon input from key people who were away – UK groups were positive on using the SLAC board, they would do software, integration • We started to derive a preliminary spec on 8/1 • Phone meeting in the next couple of weeks… • Again is useful if available in late 2008 – early 2009

Glue • We (and others) have used Araldite 2011 for gluing directly on silicon with reasonable results. • Recent results from Liverpool on n-in-p ATLAS-07 mini’s have not been good but still may questions remain… • BNL studies… • Are there differences between p-in-n and n-in-p sensors • Are there differences among vendors? • Different glues • Irradiation program is supposed to follow from this…

Glue continued • I believe program has suffered from lack of coordination • Each group has followed its own process • We need a uniform process and protocol • There are not enough samples • It is summer, people are not available • Alternate materials • Can consider thermally loading it with BN powder as in SCT • CDF used Fuller Epolite FH-5313 • Timimg is constrained by lack of samples and coordination. Note clear we will have conclusive results by NIKHEF. Hot issue…

Substrate Issues • While the ceramic hybrid has performed well it may not be a practical technology for ATLAS • Material • Cost • Flatness • Alternative is flex either bare or on a substrate • We will test this with the ABCD flex hybrid and glue it to existing 3cm sensors in a number of different configurations • Flex should arrive in September, results by NIKHEF

Ver C Copper/kapton 17 um/25 um Ver B BeO 200-250 um CC Unknown thickness Ver A Araldite 2011 50 – 75 um or alternative

Version A • Flex circuit is glued directly to the sensor with no substrate. • Issue of increased capacitance due to proximity of copper to strips: simple calculation suggest this may be less than 1 pf but needs to be checked. • Possible electrical pickup: needs to be tested. • This is the lowest mass and cheapest solution. • This version also requires specific fixtures to hold and transfer the flexible part. • We will build and test these as part of the substrate study.

Version B • CC between flex and sensor • Shares electrical issues with Version A • Perhaps (lower?) conductivity of CC helps? • Some heat spreading effect • What is thinnest CC we can find? • Following this direction is contingent upon obtaining CC samples - BNL

Version C • Use BeO as a passive substrate and heat spreader. • Strongly decouples electrical activity on hybrid from sensor, if this is an issue • Reduces capacitive effect a lot • BeO vendors can provide 100 x 20 mm substrates in 250 and probably 200 micron thickness – quoted. We are ordering these.

Bus Cable • This is wrapped up in data transmission issue • Stave 2007 is a reasonable starting model • Oxford plans a test vehicle to be fabricated soon for LVDS studies • Requirements for Stave 2008 bus • Serve a 12 module stave • BCO at 40 MHz • L1 • 24 data pairs running at 160 MHz • 4 COM pairs, each serves 3 modules • 12 HV lines

Bus Cable 2007 Signal Layout Al shield Data readout1/hybrid Clock & Command lines Port Card (passive SMC) HV distribution Serial current return Serial current link

MAX9152 LVDS (with feedback) In0 O/P0 MAX9152 O/P1 In0 LVDS In1 LVDS O/P In1 Optional Select Select MLVDS DS91D180 Serial In VDD (LVDS) HVRet Shunt Reg. Serial Out Vin Series Reg. Ret Shield/Gnd (LVDS) Dummy Hybrid • The circuit features: • 2 x LVDS inputs • One input AC-coupled (testing of balanced signalling). • The second input is AC-coupled with feedback to restore the DC at • the LVDS receiver input. This can be used for the receiving of unbalanced signals. • 1 x MLVDS AC-coupled input. • The 3 inputs can be ‘spied’ on via a second multiplexer – selectable by a jumper (data loopback). • Selectable Shunt (serial) or Parallel powering • The physical realisation of the circuit (PCB) is shown below, the dimensions (x,y) • are 39.5mm x 37.0mm. The PCB type will be a 2 layer FR4 of 1.6mm thickness, 1oz Cu with Gold/Nickel finish.

Implementation

Stave 2008 bus design Data temp Serial TTC HV

Bus Cable comments • Bus cable for Stave2007 was fabricated in 2 section (65 + 35 cm) • Cable vendor now has larger area capability and can handle the full 1.2 meter bus cable as a single part • Prepare to do a full size Stave 2008 prototype this summer/fall to test fabrication capability • If we can make this in a useful configuration for multidrop studies etc this would be an advantage • Follow-up discussion with Oxford, UCSC, others interested in data transmission and tapes. • Oxford has in-house large are fabrication capability but has expressed interest in using (our) US vendor initially.

Materials • Following the June review the material estimates have been challenged by N.Unno • Claim stave is actually more massive than supermodule • Get this if you add extra materials – CF to the facings, thick thermal epoxy layers, Al layers (unfair to do this unilaterally) • We have responded by updating and reviewing our numbers • A new table and document is in preparation, release soon • The precise material sum still depends upon various choices yet to be made – • Pipe diameter • CF material • Hybrid substrate • Thermal glues • Fom size

Mechanics • My comments here will be conceptual • Expect a number of groups to play increasingly important role here • USA East Coast collaborators • UK: Oxford, Liverpool, RAL • Geneva ? Logical but no word from them yet • Discussions between Oxford/RAL and Gil • Question of compliance, joints

Phil’s List Follows

Sensors/Irradiations A1) Implications of glue on strip-side surface. A2) Possibility of making front-side bias connection. A3) Risks associated with backplane connection and conducting epoxy (ie can a bondwire be used?) . A4) Rework implications for preserving sensor performance Comments:A1 and A2 could be studied first with miniatures while A3 and A4 would require studies with full size detectors.A1 needs miniatures with kapton glued to surface to be irradiated with gammas, protons and neutrons. Interstrip isolation to be studies with cooled chuck and connection to LHC speed electronics. A1 also needs study with full size detector cycled in temperature with large area representative kapton glued to surface to see implication of stressing silicon crystal on leakage current. For greater confidence, proton irradiation of several full-sized sensors glued with representative kapton circuit should be undertaken and evaluated at varying temperatures at least for IV characteristics.A2 could use existing irradiated miniatures. A3 and A4 would require destructive studies using first modules.If required to use conductive epoxy contact (A3) need long term programme to qualify

Bridge B1) Cross-check LBL results and understand whether concept allows rework B2) Explore single-sided bridged module concept and estimate extra material implied if rework ie detachability and independent testing and handling implied B3) Full thermal and mechanical FEA B4) Prototype with dummy components and cross-check FEA B5) Electrical prototype if required Comments:If B1 or B2 suggest this is a non-starter as the perceived advantages of the stave approach are lost or all the issues with gluing to the silicon strip face are solved satisfactorily, then programme could stop at least before steps B4 and B5. It would be useful to know if the hybrid for this has to be different or not from the standard stave.

Hybrid/Bus/Electrical C1) Converge on design of bus cable and SMC; fix location; incorporate DCS; study and optimise multi-drop LVDS C2) Define urgently connections at each end of hybrid to allow realistic electrical hybrid (but without MCC) to be developed C3) Develop system to study ASICs on 20 chip hybrid and possible first modules with direct addressing. Allow first electrical (single-sided) modules to be produced. C4) Define first test-board hybrid plus mezzanine for FPGA to allow exploration of ASIC performance in quasi-final system. Work towards greater degrees of integration/complexity and test. C5) Define specifications for MCC and any other ASICs to go on hybrid/bus C6) Design proper prototype hybrid compatible with electrical bus and on-hybrid ASICs C7) Design and fabricate all on-hybrid and on-bus ASIC chip set C8) Develop a grounding scheme for serial powering and for DCDC and chose for first prototypes C9) Define final electrical bus QA procedure C10) Fabricate final electrical bus and test C11) Define specifications for SMC card including ASIC and opto+electrical outputs C12) Define stave carrier box which accommodates wirebonding and procure enough for full assembly

Hybrid…. C13) Assembly of single-sided objects and attachment to electrical bus and progressively test C14) Irradiate single-sided objects on short stave sections C15) Define and prototype corresponding petal/forward stave (with all the additional procurement of varying components that this implies) C15) Studies of electrical cross-talk and HV multiplexing (both petal and stave) C16) Initiate studies on robotic assembly to ensure uniform tolerances and efficiency (Edge alignment; robotics and survey should all be used -not alternatives) Comments:The items are in some sort of possible chronological order but this is not a project plan as it stands. One of the key issues that relates to all aspects is risk analysis. The rework requirements depend on what is the most likely or most harmful failure mechanism. The QA is vital.Repair scenarios for damage to hybrids, the bus or other items should be defined and the number of items sacrificed to make a repair evaluated as part of the risk estimation. An important issue is to irradiated and test "modules" (C14) and to integrate this into a more cohesive irradiation programme with chips and sensors. C15 represented a huge programme for which there is insufficient effort. Hopefully the outer barrels do not need any special effort but there may be optimisations there to take advantage of the lower power density and lower cooling required for the sensors.

Mechanical D1) More work needed on the mechanical (FEA) aspects of stave eg natural frequencies, thermal cycling, stiffness, implications of stainless cooling pipe D2) Fabrication of multiple examples of stave support with embedded cooling using stainless pipes D3) Prototyping studies: natural frequencies, stiffness of structures, internal inspection after thermal cycling (stress on poco foam), CME studies, mechanical role of silicon.(Experimental program to understand the shear forces arising from the foam/pipe/carbon structure. Study what is happening using ultrasound and/or X-rays) D4) End insertion detailed proposal for stave and prototyping of system D5) Develop tooling and get experience with double-sided stave D6) Define cooling solution (CO2?) D7) Assemble mechanical stave with as many final items as possible and exercise fully assembly and handling procedure, then use for FEA cross-checks. D8) Carry out corresponding work on petal/forward stave prototype D9) Risk or fault analysis - cooling tubes, electrical bus & module failure D10) Interact with Engineering group to define quantity and topology of services Comments:If CO2 is adopted, the stiffness of the stave with thickness appropriate to CO2 should be revaluated. Also under D1 and D3, the stainless steel to pocofoam interface needs explicit prototyping. There should be a programme (D7) resulting in multiple highly realistic "mechanical“ staves fitted with heater elements for a variety of assembly (includingwire-bonding), handling, mounting and mechanical plus thermal FEA cross-checks.

Stave Status and Plans