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RISC

RISC. By Omar Hernandez CS147. CISC. RISC. Types of CPUs. Complex Instruction Set Computers. Reduced Instruction Set Computers. Types of CPUs. CISC. Have large instruction sets that are close to higher language structures Examples of CISC: Intel’s Pentium- class CPUs

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RISC

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  1. RISC By Omar Hernandez CS147

  2. CISC RISC Types of CPUs

  3. Complex Instruction Set Computers Reduced Instruction Set Computers Types of CPUs

  4. CISC • Have large instruction sets that are close to higher language structures • Examples of CISC: • Intel’s Pentium- class CPUs • Motorola 68000 CPUs

  5. RISC • Reduced • Instruction • Set • Computing

  6. RISC • Instruction set for RISC processors are: • Simple • Pure Assembly language dedicated to the design of the CPU

  7. RISC Features • Fixed length Instructions • Limited Loading and Storing Instructions Access Memory • Fewer Addressing Modes • Instruction Pipeline • Large Number of Registers • Hardwired Control Unit

  8. RISC Features (Cont’d) • Delayed Loads and Branches • Speculative Execution of Instructions • Optimizing Compiler • Separate Instruction and Data Streams

  9. RISC Instruction Sets • In general have only up to 100 instructions in their set • Each instruction is capable of being executed in a single clock cycle

  10. RISC Instruction Sets (Cont’d) • Basic Instructions include: • Data move (load, store, & register move) • Arithmetic • Logic • Shift • Branch (jumps)

  11. RISC Instruction Sets (Cont’d) • RISC CPUs operate usually on two data types: • Integer • Floating point • Using different precisions or numbers of bits within a given data type • Using these basic data types, you can program into more complex data types

  12. RISC Instruction Sets (Cont’d) • RISC CPUs use different instruction formats • Every instruction must have same amount of bits regardless of format • CPU must be able to access each instruction code in a single memory-read operation in order to facilitate pipelining

  13. RISC Instruction Sets (Cont’d) • Instruction set usually has different types of load and store due to bit alignment using from • 8 bit • 16 bit • 32 bit • Etc.

  14. RISC Instruction Sets (Cont’d) • Addressing modes all depend on clock cycle • Without it you would have to redesign pipeling used to process instructions

  15. RISC Instruction Sets (Cont’d) • RISC II CPUs have: • 3 primary memory addressing modes • Indexed address mode • Register indirect address mode • Contain a pseudoregister R0 that’s always zero

  16. RISC Performance • RISC uses two techniques to improve performance: • Instruction Pipeline • Register Window & Renaming

  17. RISC Performance (Cont’d) • Instruction Pipeline • Breaks down fetch-decode-execute process into several instructions in parallel • Pipeline allows one instruction per clock cycle

  18. Instruction Pipeline

  19. Instruction Pipeline (Cont’d)

  20. Instruction Pipeline (Cont’d)

  21. Instruction Pipeline (Cont’d)

  22. Instruction Pipeline (Cont’d) • Speedup is the ratio of time needed to process n instructions using nonpipelined control unit to the time needed using a pipelined control unit with the following formula:

  23. Instruction Pipeline (Cont’d) • is time needed to process 1 instruction using a nonpipelined control unit • is number of stages in pipeline • is clock period of the pipeline • Example:

  24. Instruction Pipeline Requirements • RISC CPU must include cache memory that is at least as fast as the pipeline • Cache must separate instructions and data to avoid memory conflicts from stages of pipeline • Compiler has to be optimized to reorder instructions in order to avoid problems with branch instructions

  25. Register Windowing & Renaming • Takes advantage of large amounts of registers that RISC CPUs have • Producing more hits to register than memory • Thus producing faster CPU performance

  26. Types of registers • Global register – always accessible • Windowed register – a subset accessible at any specific time

  27. MIPS register organization

  28. Register Renaming • Makes use of any group of register with pointers • Doesn’t follow a register convention which assigns registers to a certain task

  29. Instruction Pipeline Conflicts • Data Conflicts • Software fixes • No-op insertion • Instruction reordering • Hardware fix • Stall insertion • Data forwarding • Branch Conflicts

  30. Data Conflicts

  31. No-Op Insertion

  32. Instruction Reordering

  33. Stall Insertion

  34. Data Forwarding

  35. Branch Conflicts • Solutions • No-op insertion • Instruction reordering • Annulling • Branch prediction

  36. Branch Conflicts (Cont’d) • Annulling • Instructions proceed through the pipeline as they normally would. If an instruction should not have been executed, because a previous instruction branched away from it, its results are not stored.

  37. Branch Conflicts (Cont’d) • Branch Prediction • Allows the compiler or pipeline hardware to make an assumption as to whether or not the conditional branch will be taken.

  38. RISC vs. CISC • Each type of processor has its benefits • Depends what type of device to be built • If it’s a small device • RISC • If it’s a large device • CISC

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