Virtual Prototyping with Carbon Design Tools

1. Virtual Prototyping with Carbon Design Tools Aalap Tripathy, Rabi Mahapatra Embedded Systems Codesign Lab http://codesign.cse.tamu.edu

2. Overview • SoC’s today • SoC design paradigm • SoC design issues • Virtual prototyping benefit • Virtual Prototyping options • What is a “Carbon model”? • Tools used & their interplay • Assignments Flow • Resources

3. Overview • SoC’s today • SoC design paradigm • SoC design issues • Virtual prototyping benefit • Virtual Prototyping options • What is a “Carbon model”? • Tools used & their interplay • Assignments Flow • Resources

4. SoC’s today Single chip DVR- 4 channel MPEG 4 DVR SoC

5. SoC’s today 802.11b radio, MAC, baseband processor, pn-chip flash, ARM Applications Processor

6. SoC’s today Tablet/Smart TV/Thin Client SoC – ARM Applications Processor, Video Interface, CMOS Sensor Input, USB, Audio Interface (I2S, S/PDIF), SPI, I2C, UART, GPIOs

7. SoC’s today Smartphone/Tablet SoC – ARM Mali 400 (single core) graphics card, Video Processing Unit, Audio Interface, Webcam Interface, Video Interface etc.

8. SoC’s today Server SoC – ARM Quad Core

9. Overview • SoC’s today • SoC design paradigm • SoC design issues • Virtual prototyping benefit • Virtual Prototyping options • What is a “Carbon model”? • Tools used & their interplay • Assignments Flow • Resources

10. SoC design paradigm • System Realization • System requirements defined in h/w and s/w • SoC Realization • Architecture for semiconductor defined • IP blocks chosen • Design matured • Silicon Realization • Design implemented in Silicon • Concerns for SoC Architect • How to validate SoC design? • How to reduce risk? – Reuse IP • How to convey design intent to software development team? – Design is still in flux. • How to convey design impact to end-customer? – Black-box parts of design • How to quickly detect system corner cases?

11. SoC design paradigm

12. Overview • SoC’s today • SoC design paradigm • SoC design issues • Virtual prototyping benefit • Virtual Prototyping options • What is a “Carbon model”? • Tools used & their interplay • Assignments Flow • Resources

13. SoC design issues IP Selection • Which vendor? • Which IP? • Will they all play together? USB3 CPU(s) GPU Ethernet MIPI HDMI WLAN GPIO PCIe UART Without Cycle Accurate Modeling • Forced to believe IP marketing • SoC may not meet spec • Can’t benchmark till purchase

14. SoC design issues USB3 CPU(s) GPU Ethernet Periph Fabric/NoC MIPI HDMI WLAN CCI/NoC NoC/Fabric GPIO PCIe UART Interconnect Architecture • CCI vs. NOC vs. Fabric? • Make or buy? • How many? • What configuration(s)? Without Cycle Accurate Modeling • No validation between layout and performance • Inefficient power consumption • Missed performance spec • Waste power with overdesign

15. SoC design issues USB3 CPU(s) GPU Ethernet Periph Fabric/NoC MIPI HDMI L2 Cache WLAN CCI/NoC NoC/Fabric GPIO DDRx PCIe UART Memory subsystem • Cache sizing • How big? • Which memory technology? • System performance impact? Without Cycle Accurate Modeling • Wasted die space on overdesigned cache • Poor cache performance • Overspend on IP • Wasted power

16. SoC design issues USB3 CPU(s) GPU Ethernet Periph Fabric/NoC MIPI HDMI L2 Cache WLAN CCI/NoC NoC/Fabric GPIO DDRx PCIe UART Firmware Development • Pre-silicon firmware development • Software performance analysis • System integration issues Without Cycle Accurate Modeling • No guarantee of software running on first day silicon • Inability to tune hardware/ software performance • Chip re-spin – huge cost

17. SoC design issues Internal Users External Users USB3 USB3 CPU(s) CPU(s) GPU GPU Ethernet Ethernet Periph Fabric/NoC Periph Fabric/NoC MIPI MIPI HDMI HDMI L2 Cache L2 Cache WLAN WLAN CCI/NoC CCI/NoC NoC/Fabric NoC/Fabric GPIO GPIO DDRx DDRx PCIe PCIe UART UART Deployment • Secure platform for external users Without Cycle Accurate Modeling • Can’t black-box feature sets. • Can’t share with end customer • IP exposure • Design intent lost

18. Overview • SoC’s today • SoC design paradigm • SoC design issues • Virtual prototyping benefit • Virtual Prototyping options • What is a “Carbon model”? • Tools used & their interplay • Assignments Flow • Resources

19. Virtual Prototyping Benefit

20. Prototyping Options

21. Overview • SoC’s today • SoC design paradigm • SoC design issues • Virtual prototyping benefit • Virtual Prototyping options • What is a “Carbon model”? • Tools used & their interplay • Assignments Flow • Resources

22. What is a Carbon Model? • What is a Carbon Model? • A high performance linkable software object • Generated by proprietary compiler from • synthesizable RTL design files • options & directives files • Contains cycle-accurate & register-accurate description of hardware design • Organized in the form of: • Software Object file (libdesign.a on Linux or libdesign.lib on Windows) • Header file (libdesign.h) • Binary database (libdesign.symtab.db) – database with information about all internal signals • Using a Carbon Model • Linked with gcc (or Microsoft VC++) • Libcarbon5.so & carbon_capi.h are part of installation on Linux • Simulator communicates with hardware model through sockets using carbon_capi.h

23. Tools you will be using http://www.carbondesignsystems.com/carbon-model-studio/ http://www.carbondesignsystems.com/soc-designer-plus/ http://www.carbondesignsystems.com/performance-analysis-kits/ Carbon Model Studio • Enables carbon model creation from RTL • Verilog/VHDL/SystemC CPAK • Carbon Performance Analysis Kits • Ready-to-use assembly of processor models + IP blocks + baremetal/OS + benchmarking tools Carbon SoC Designer • Virtual Prototyping Canvas • Assemble system • Drive system • Debug • Analyze (profile) • Optimize

24. Interplay between tools State Machine design Firmware development/source code RTL Other IP Models μPModel CA Model System Level Model LT Model CA Model LT Model Co-simulation

25. What will tools enable? Architectural Analysis • Analyze memory subsystems • Analyze cache statistics • Analyze system throughput & latency • Validate bus & pipeline performance assumptions • Zero silicon design & validation • Validate HW/SW partitions • Software function profiling • Synchronization & timing • Will arbitration logic work as expected? • Enables quick re-configurability & re-run of SoC design • Feature change is easy

26. What will tools enable? Firmware Validation & Application software development • Begin firmware development even while SoC is in “concept” stage. • Use the same platform as SoC hardware & software designs mature • Maximize design reuse • Integrated debug tools for hardware & software • Analyze impact of software on hardware performance & vice versa • Have complete system visibility • Set breakpoints in firmware debugger or in hardware • Interrupt SoC operation at any point to examine behavior

27. Overview • SoC’s today • SoC design paradigm • SoC design issues • Virtual prototyping benefit • Virtual Prototyping options • What is a “Carbon model”? • Tools used & their interplay • Assignments Flow • Resources

28. Assignments Flow • Introduction to SoC Designer • Construct & Debug an ARM Cortex A9 Bare-metal SoC • Understand the role of IP blocks/components necessary to design a system • Run an example sort application (insertion & bubble sort) • Introduction to Model Studio • Create a carbon model from RTL (Vectored Interrupt Controller) • Write RTL for a APB compatible timer, create carbon model, integrate into ARM Cortex A9 Baremetal SoC • Introduction to Co-simulation • Export Interrupt Controller signals into Modelsim simulation kernel from SoC Designer. • Use Interrupt Controller RTL & Top level test-bench to drive SoC Designer • Perform co-simulation for APB compatible timer • Compilation & Simulation of Applications • How to create, compile, run and characterize an application on SoC Designer • “Hello World” & Vector multiplication – How to create an ARM Executable file (axf) • Profile software code, observe bus level transactions & correlate to source code 1 2 3 4

29. Interplay between tools State Machine design Firmware development/source code 0 1 2 RTL Other IP Models 4 μPModel CA Model System Level Model LT Model LT Model LT Model 3 Co-simulation

30. Example ARM Cortex A9 Demo SoC • ARM application processor connected via an AXIv2 bus to program & data memory. Memory mapped IO • Bridge to APB bus  connects to timer, Bridge to AHB bus  connects to interrupt controller • Core for processor compiled from ARM RTL, supports 32 kb Instruction Cache, 32kb Data cache, 128 KB TLB, no Floating Point Unit, does not contain Neon Media Processing Engine • AMBA – de-facto standard for on-chip communication, open standard – Learn more.

31. Who else is using these tools?

32. Resources • ARM InfoCenter - http://infocenter.arm.com/ • Carbon Tutorials - /opt/carbon_tutorials • Component User Guides - /opt/documents • ARM Specs - /opt/documents/arm_specs/ • Carbon Tool User Guides - /opt/SoCDesigner/doc/ • ModelSim User Guide - /opt/ModelSim-SE-10.d/modeltech/docs/pdfdocs/modelsim_se_tut.pdf • Please DO NOT register on Carbon Design Systems website. The models you may need for projects will be provided to you • Contact for tool-related issues: • Prof. Rabi Mahapatra (rabi@cs.tamu.edu) • DeamIeong (deam_ieong-0814@tamu.edu)

33. Conclusion • Virtual prototyping tools can help accelerate • Architectural exploration • Firmware development • System integration & customer integration • Familiarity & expertise with these tools will help • Job-relevant skills • Gain experience with ARM-based SoC, AXI • Experience switched fabrics and network topology

34. Acknowledgement