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Fast Timing-Model Independent Buffered Clock-Tree Synthesis

Fast Timing-Model Independent Buffered Clock-Tree Synthesis. Xin -Wei Shih and Yao- Wen Chang. Outline. Introduction Problem formulation Algorithms Experimental results Conclusions. Introduction.

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Fast Timing-Model Independent Buffered Clock-Tree Synthesis

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  1. Fast Timing-Model Independent Buffered Clock-TreeSynthesis Xin-Wei Shih and Yao-WenChang

  2. Outline • Introduction • Problem formulation • Algorithms • Experimental results • Conclusions

  3. Introduction • Skew-minimized buffered clock-tree synthesis plays an important role in high-performance VLSI designs for synchronous circuits. • Due to the insufficient accuracy of existing timing models for modern chip design, embedding simulation process into a clock-tree synthesis flow becomes inevitable.

  4. Introduction • A possible way to improve the speed is performing the clock construction by structure optimization. • Mesh • In this paper, a novel timing-model independent buffered clock treesynthesis method is proposed. • Buffering and wiring structures of all paths from the clock source to its sinks are almost the same.

  5. Problem formulation • Problem: Buffered Clock-Tree Synthesis (BCTS) • Instance: Given a set of clock sinks, a slew-rate constraint, and a library of buffers. • Question: Construct a buffered clock tree to minimize its skew, subject to no slew-rate violation.

  6. Algorithm

  7. Branch-Number Planning • The number of leaves (sinks) can be treatedas a multiplication sequence of branching. • This multiplication sequenceexactly forms a factorization. • Then, the BNP is arranged in the non-increasing order1 of thefactorization list.

  8. Branch-Number Planning

  9. Tree Construction-Partitioning • A top-down manner like [10]or a bottom-up one like [7, 11], they can hardly apply to nonbinarytree structures. • Therefore, we propose a novel partitioningmethod, which can not only handle non-binary tree structures, butalso achieve good quality in terms of the cluster diameter. • cluster diameter : the maximum distance among sub-trees withinthe same cluster.

  10. Partitioning • We borrow the idea of cake cutting, i.e., slicinga cake into pieces from the center of the cake.

  11. Embedding-Region Construction

  12. Node Embedding

  13. Pseudo Sink Handling • Since the identical branch numbers at the same levelare required in the symmetrical structure, a pseudo sink should betransformed into a dangling wire to maintain the symmetry. • For partitioning,we relax that the sizes of clusters in a partition can differ by atmost one for the first recursion. • For nodeembedding, we let the embedding regions of pseudo sinks cover theentire chip.

  14. Buffer Insertion • A top-down manner • By tracing along the tree edges, oncethe slew rate is about to violate the constraint, identical buffersare inserted for all branches. • Insert identical buffers in terms of the typeand the size at the same level. • The slew rate is approximated byaccumulated capacitance starting from the latest inserted buffer.

  15. Buffer Insertion

  16. Experimental results • Implemented in the C++ programming language on a 2.6 GHz AMD-64 workstation. • Four ISPD’09 Clock Network Synthesis Contest benchmarks with no blockages [17] and the IBM benchmarks [19]. • Use ngspice [13] simulation based on the 45nm process technology [14] to evaluate the quality.

  17. Experimental results • clock skew (skew) • clock-latency range(CLR) • total resource usage (usage)

  18. Experimental results

  19. Experimental results

  20. Conclusions • We have presented a fast timing-model independent buffered clock tree synthesis method to construct a symmetrical clock tree with little wiring overhead. • By symmetrically constructing a clock tree, the clock skew can be minimized without referring to simulation information.

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