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Compiler Back End Panel

Compiler Back End Panel. Robert Geva Intel Compiler Lab. Back End Compiler Panel. 1) Are compiler code generation techniques going to transition along with the hardware transition from multi-core to many-core and hybrid systems and at what speed?

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Compiler Back End Panel

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  1. Compiler Back End Panel Robert Geva Intel Compiler Lab

  2. Back End Compiler Panel • 1) Are compiler code generation techniques going to transition along with the hardware transition from multi-core to many-core and hybrid systems and at what speed? • 2) What information do you need from a Compiler Intermediate Format to efficiently utilize multi-core, many-core and hybrid systems that is not available from traditional languages like C, C++, or F90? Are you looking at directive-based or library-based approaches or is there another approach that you like? • 3) Is embedded global memory addressing (like Co-Array Fortran) to be widely available and supported even on distributed memory systems? • 4) What kind of hybrid systems or processor extensions are going to be supported by your compiler's code generation suite? • 5) What new run-time libraries will be available to utilize multi-core, many-core, and hybrid systems and will they work seamlessly through dynamic linking?

  3. Are compiler code generation techniques going to transition along with the hardware transition from multi-core to many-core and hybrid systems and at what speed? • JIT compilingCt: Research technology fora data parallel language • Forward scaling to future architectures • Save costly memory copyingby delayed code generation Validation Multipletargets

  4. Are you looking at directive-based or library-based approaches or is there another approach that you like Is “limit” loop invariant? Needs more work Here’s my code Interactive Compiler technology to Guide the programmer to write serial codewith directives and restructuring, leading to automatic parallelism

  5. Is embedded global memory addressing (like Co-Array Fortran) to be widely available and supported even on distributed memory systems?

  6. What kind of hybrid systems or processor extensions are going to be supported by your compiler's code generation suite? Existing SIMDSSE, SSE2, SSE3, SSE4 LRB new instructions512 widthMasked operations Broadcasts, swizzles Advanced Vector eXtensions256 width 3 operand, non destructiveEnhanced data re-arrangement

  7. What new run-time libraries will be available to utilize multi-core, many-core, and hybrid systems and will they work seamlessly through dynamic linking? • Resource coordination and task scheduling • http://channel9.msdn.com/pdc2008/TL22/ • Generic algorithms, equivalent to language extensions • Domain specific libraries • Including math libraries • New domains, natural language processing, gesture recognition • DLL hell? No good news

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