ECE 4110– Sequential Logic Design

1. ECE 4110– Sequential Logic Design Lecture #25 • Agenda • More on State Machines in VHDL • Announcements • HW #11 due. • HW #12 assigned.

2. State Machines in VHDL • Next State Logic “F”- we use another process to construct “F”

3. State Machines in VHDL • Next State Logic “F”- the process will be combinational logic NEXT_STATE_LOGIC : process (In, Current_State) begin case (Current_State) is when S0 => if (In=‘0’) then Next_State <= S0; elsif (In=‘1’) then Next_State <= S1; end if; when S1 => if (In=‘0’) then Next_State <= S2; elsif (In=‘1’) then Next_State <= S0; end if; when S2 => if (In=‘0’) then Next_State <= S0; elsif (In=‘1’) then Next_State <= S3; end if; when S3 => if (In=‘0’) then Next_State <= S0; elsif (In=‘1’) then Next_State <= S0; end if; end case; end process;

4. State Machines in VHDL • Output Logic “G”- we use another process to construct “G”- the expressions in the sensitivity list dictate Mealy/Moore type outputs- for now, let’s use combinational logic for G (we’ll go sequential later)

5. State Machines in VHDL • Output Logic “G”- Mealy type outputs OUTPUT_LOGIC : process (In, Current_State) begin case (Current_State) is when S0 => if (In=‘0’) then Found <= 0; elsif (In=‘1’) then Found <= 0; end if; when S1 => if (In=‘0’) then Found <= 0; elsif (In=‘1’) then Found <= 0; end if; when S2 => if (In=‘0’) then Found <= 0; elsif (In=‘1’) then Found <= 0; end if; when S3 => if (In=‘0’) then Found <= 0; elsif (In=‘1’) then Found <= 1; end if; end case; end process;

6. State Machines in VHDL • Output Logic “G”- Moore type outputs OUTPUT_LOGIC : process (Current_State) begin case (Current_State) is when S0 => Found <= 0; when S1 => Found <= 0; when S2 => Found <= 0; when S3 => Found <= 1; end case; end process;- this is just an example, it doesn’t really work for this machine

7. State Machines in VHDL • Example- Let’s design a 2-bit Up/Down Gray Code Counter using User-Enumerated State Encoding- In=0, Count Up- In=1, Count Down- this will be a Moore Type Machine- no Reset

8. State Machines in VHDL • Example- let’s collect our thoughts using a State/Output Table Current_State In Next_State Out CNT0 0 CNT1 00 1 CNT3 CNT1 0 CNT2 01 1 CNT0 CNT2 0 CNT3 11 1 CNT1 CNT3 0 CNT0 10 1 CNT2

9. State Machines in VHDL • Examplearchitecture CNT_arch of CNT is type State_Type is (CNT0, CNT1, CNT2, CNT3); signal Current_State, Next_State : State_Type; begin STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') then Current_State <= Next_State; end if; end process; NEXT_STATE_LOGIC : process (In, Current_State) begin case (Current_State) is when CNT0 => if (In=‘0’) then Next_State <= CNT1; elsif (In=‘1’) then Next_State <= CNT3; end if; when CNT1 => if (In=‘0’) then Next_State <= CNT2; elsif (In=‘1’) then Next_State <= CNT0; end if; when CNT2 => if (In=‘0’) then Next_State <= CNT3; elsif (In=‘1’) then Next_State <= CNT1; end if; when CNT3 => if (In=‘0’) then Next_State <= CNT0; elsif (In=‘1’) then Next_State <= CNT2; end if; end case; end process; OUTPUT_LOGIC : process (Current_State) begin case (Current_State) is when CNT0 => Out <= “00”; when CNT1 => Out <= “01”; when CNT2 => Out <= “11”; when CNT3 => Out <= “10”; end case; end process;end architecture;

10. State Machines in VHDL • Example- in the lab, we may want to observe the states on the LEDs- in this case we want to explicitly encode the STATE variablesarchitecture CNT_arch of CNT is subtype State_Type is BIT_VECTOR (1 dowto 0); constant CNT0 : State_Type := “00”; constant CNT1 : State_Type := “01”; constant CNT2 : State_Type := “10”; constant CNT3 : State_Type := “11”; signal Current_State, Next_State : State_Type;