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Finding the root cause of ESD problems

Finding the root cause of ESD problems . Dr. David Pommerenke With contributions from all members of the EMC laboratory University Missouri Rolla – EMC laboratory pommerenke@ece.umr.edu. Content. ESD is combines many tests in one test ESD failure analysis Susceptibility scanning

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Finding the root cause of ESD problems

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  1. Finding the root cause of ESD problems Dr. David Pommerenke With contributions from all members of the EMC laboratory University Missouri Rolla – EMC laboratory pommerenke@ece.umr.edu # 1

  2. Content • ESD is combines many tests in one test • ESD failure analysis • Susceptibility scanning • Voltage in traces during ESD testing # 2

  3. Definitions Hard-error: Any error that leads to a physical failure of the IC. (Excessive leakage current, loss of functionality) Soft-error: Any error that can be cured by resetting the system (logical errors: bit error, false reset) # 3

  4. Physical parameters that may lead to an ESD failure ESD combines many different tests into one test standard. From electrostatics, via breakdown physics to a 1 GHz 20kV/m pulse. # 4

  5. It has failed! - What to do now? • It failed, what now? • Is it a soft or a hard failure? • At which test point did it fail? • At which voltage did it fail? • Was it in contact or air discharge mode? • How repeatable is the failure? Question: What do you do to debug ESD problems? # 5

  6. How to fix it? Exact circuit understanding Pro: The most cost efficient solution. Learn how to design in the future. Contra: Need to understand software Need to understand circuits Requires specialized equipment May require special firmware Shielding Pro: No system understanding needed. If it works, the fast! Contra: Often more expensive solution Adds material But how to do it? # 6

  7. Local probing around the EUT A first start of finding the root cause may be: @ 8kV, restart EUT display 20mm 50mm @ 10kV restart 200mm @ 15kV restart • Locating sensitivity on the outside might help to correlate to the affected IC or trace, but: • Outside location may only be a result of breach in shielding • Outside location is too broad to correlate to details inside: Let’s go inside! # 7

  8. Different coupling mechanisms require different probes • Injection can be done: • To the enclosure • To cables • To connectors • To boards • To board traces • To lead-frames traces - dm - cm - mm - cm2 - 5 mil (using microscope) - 1 mil (using microscope) # 8

  9. Probes used for injection # 9

  10. Different coupling mechanisms require different probes Direct injection between to “grounds”. In selecting the right injection method one has to try to emulate the same excitation mechanism as occurs during the standardized test or at the customer site. Anticipating the right method is often guided by carefully observing the differences of failure signature at different test points. # 10

  11. Disturbance sources: TLP and narrow pulse The measurement of the high voltage transmission line pulse generator output pulse, about 500 ps rise (20-80%) Less than 200 ps pulse Narrow pulse generator # 11

  12. Automated Susceptibility Scanning system of UMR Brief explanation The system moves injection probes to predefined locations, injects pulses and observes the system response. In most cases, pulses are “ESD-like”, e.g., having rise times 0.1 -2 ns. Injection is done using different injection probes for testing direct coupling, E and H-field coupling. If needed, the voltages at the input of the IC are measured during the ESD event. # 12

  13. Automated Susceptibility Scanning system of UMR TLP triggering signal TLP Motion Control Probe position data, motion control Power S/W Control Computer Scope signal probing Pulse injection System monitor (parallel port) Critical is the error feedback: A test code needs to be operating on the EUT. The test code signals to the control PC if a malfunction has occurred. If so, the level of injected noise (by source setting, not by induced voltage) is recorded and the EUT is reset. # 13

  14. Test flow diagram # 14

  15. 310 310 310 310 300 300 300 300 290 290 290 290 280 280 280 280 450 270 270 270 270 400 260 260 260 260 350 300 250 250 250 250 250 240 240 240 240 50 100 150 200 250 180 190 200 210 220 230 240 250 180 190 200 210 220 230 240 250 180 180 190 190 200 200 210 210 220 220 230 230 240 240 250 250 Example: Identifying sensitive nets • Besides direct coupling to an IC, four sensitive nets are identified • Only 4 nets are sensitive, but there sensitivity is 10X as strong as any other net Net 2 Net 4 Net 2 Net 1 Net 3 Net 4 Net 3 Net 1 # 15

  16. 310 Probe Polarization : ← 300 290 Scanned in next stage 280 270 260 250 240 180 190 200 210 220 230 240 250 Example: Identifying sensitive nets The same area is scanned using different polarization of the H-field probe. The difference between the “left” and the “right” polarization is the polarity of the induced noise voltage. The sensitive traces are identified by circuit diagram. If needed a finer scan is performed. # 16

  17. 256 254 252 250 248 246 244 242 240 238 178 180 182 184 186 188 190 192 194 1.5mm 1mm Example: Identifying sensitive nets • A critical part of the board in the previous scanned area has been fine-scanned using very small magnetic field probe to identify the correct trace • The scan resolution was set to 0.5mm x 0.5mm • The small probe couples less energy into the trace, but in a highly localized area # 17

  18. 310 310 310 310 300 300 300 300 290 290 290 290 280 280 280 280 450 Net 2 270 270 270 270 400 Net 3 260 260 260 260 350 Net 2 300 250 250 250 250 Net 1 250 240 240 240 240 50 100 150 200 250 190 200 210 220 230 240 250 180 180 190 200 210 220 230 240 250 190 190 200 200 210 210 220 220 230 230 240 240 250 250 180 180 Modification to a sensitive net Net 2 Net 3 Net 1 Net 2 • After comparing the identified sensitive nets with PCB layout, three nets have been identified to be sensitive to ESD • The sensitivity of those nets have been quantified in terms of applied voltage in the HV generator • Induced current direction on the each sensitive net has been identified # 18

  19. Modification to a sensitive net Simple Low Pass TX 100ohm RX 330pF Filter Location # 19

  20. 460 460 440 440 420 420 400 400 380 380 360 360 340 340 320 320 300 300 280 280 260 260 60 80 100 120 140 160 180 200 220 240 260 260 60 80 100 120 140 160 180 200 220 240 Modification to a sensitive net Before After Filter location # 20

  21. 310 305 300 295 290 285 280 275 70 75 80 85 90 95 100 105 Direct coupling to ICs Medium Magnetic Probe Scanned Area • The top side of the PCB is scanned using the medium size magnetic probe with four different polarization • Some sensitive areas on the IC are identified # 21

  22. Direct coupling to ICs Signal couples directly into the IC IC reacts to narrow pulses much narrower than the intended signals 300ps • For such an ICs, no PCB or shielding solution is economical. • Scanning can identify such situations and help to verify improvements • in the IC design, packaging (e.g., flip-chip) or the control software. • In our experience, direct coupling to ICs is growing problem: • Fast IC process technology is used more and more in badly shielded products. • Coupling to PCBs is reduced by burried layers and traces • Dense PCBs have hardly any traces visible (BGA packages) # 22

  23. New is better, well …. Shown are the voltage settings of a pulse generator at which an upset occurs if A narrow pulse (less than 300 ps width at 50% amplitude) is causing an upset of the IC. Note: the new IC performed worse! Worsening ESD soft-error performance is a significant risk if new processes are introduced, or if I/O structures are modified. # 23

  24. Voltages on traces # 24

  25. How measure in-circuit while pulsing? Semi rigid coax cable, connected to 20GS/sec 6 GHz bandwidth scope The trace is loaded by 470 + 50 Ohm. The small loop area ensures little dB/dt coupling and good frequency response of the probing method. GND VIA (close to the Trace) 470 Ohm # 25

  26. 1.4 Coaxial Probe connects to another IC 56pF attached here 1.2 75ohm IC of interest 100pF connects to another IC 1000 Voltage[V] 1 75ohm 75ohm Pulse injection here 0.8 56pF 0 1 2 3 4 5 Time [ns] Inner layer trace Voltages on a status line Very Narrow pulse on slow status line (< 150ps) leads to crash • Three traces have been isolated by terminating/filtering circuits • Double pulse has been eliminated • The reset line still reacts to this narrow pulse (the system crashed) • It has been shown that the IC of interest is causing the crash, reacting to a very narrow pulse # 26

  27. Differential clock Clock_N (Ch 1 on scope) 290 290 290 290 315 315 315 315 285 285 285 285 310 310 310 310 280 280 280 280 305 305 305 305 Clock_P (Ch 2 on scope) 300 300 300 300 275 275 275 275 295 295 295 295 270 270 270 270 200ps pulse injection here! 290 290 290 290 265 265 265 265 285 285 285 285 200 202 206 208 210 212 214 216 218 200 200 200 208 208 208 208 202 202 202 210 210 210 210 204 204 204 204 212 212 212 212 206 206 206 214 214 214 214 208 208 208 216 216 216 216 210 210 210 218 218 218 218 212 212 212 220 220 220 220 214 214 214 222 222 222 222 216 216 216 224 224 224 218 218 218 224 Clock_N Clock_P Pulse has been applied repeatedly, increasing the voltage until system crashes Waveforms are recorded (20 GHz / 6 Gsample/sec). # 27

  28. -5V, on DP, crashed - 2 0.8 0.4 Voltage on trace [V] 0 0 10 20 Voltage difference 1 Voltage[V] 0 -1 0 10 20 crash Time [ns] ESD Event on differential clock Very sensitive to noise during the transition # 28

  29. -8V, on DP, Crashed - 2 20V, on DP, Not crashed - 1 1 2 1 Voltage on trace [V] Voltage on trace [V] 0 0 0 4 8 12 16 20 0 4 8 12 16 20 Voltage difference Voltage difference 1 1 Crash threshold : approx. 0.2V 0 0 Voltage[V] Voltage[V] -1 -1 0 4 8 12 16 20 0 4 8 12 16 20 crash Crash threshold: approx. 0.2V Time [ns] Time [ns] ESD Event on differential clock No crash! Clock_P + Differential input has an offset Clock_N - # 29

  30. Noise increased differential voltage The result is repeatable. Increasing difference should not lead to a system crash. Why? # 30

  31. 2 1 Voltage on trace [V] 0 0 4 8 12 16 20 Voltage difference 1 Voltage[V] 0 -1 0 4 8 12 16 20 Time [ns] ESD on differential clock – Common Mode disturbance No crash If the common mode voltage is relatively low, the differential input will suppress the common mode signal. 2x330 # 31

  32. Common mode: Not crashed no crash no crash No crash, although the differential signal is already strongly disturbed # 32

  33. crash Common mode: Crashed 120V from the HV generator was injected on both Clock_P and Clock_N  Crashed Differential Mode is about as robust as single ended signaling. Design details matter: (conversion, common mode termination etc.) # 33

  34. Voltage surpasses threshold for a sufficiently long time Linear network, bond wire inductance and input capacitance, ring or peak the pulse, leading to a softerror. Voltage triggers non-linear effect on the input buffer Voltage causes ESD protection to forward bias, causes substrate injection or internal power fluctuations, leading to crash Current leads to latch-up, or latch-up like situation. How an IC can react to pulses # 34

  35. Open Questions • Immunity problems caused by global coupling vs. local coupling to one trace. • Correlation system level – board level. • IC level immunity test methods and robustness guidelines for IC design are not well developed yet. • IC level immunity standards. • Software for improving immunity. • Latch-up and ESD protection circuit recovery, how many of the observed soft errors are caused by latch-up? # 35

  36. Conclusion • Using local injection the disturbed traced can be identified. • The sensitivity of I/O ports can be quantified. • These data can be used to analyze the function of circuits designed to reduce ESD sensitivity. • In-circuit measurements can be done while doing local injection, as the amount of common mode signal is vastly reduced. This is a developing field, many questions are still out there, just waiting to be solved. # 36

  37. IC and system level ESD testing IC ESD System level ESD Consequence Standard Voltage DUT Operating? Application method Tested properties When does it occur? Destructive CDM / HBM / MM Typically < 3000 IC, sub system System is not powered Direct to the IC PINs IC protection circuits Manufacturing, handling Destructive and Upset IEC 61000-4-2 Typically < 15 000 System System is operating Enclosure, PINs System design Qualification tests, Customer site # 37

  38. Induced Currenton the net Probe Polarization Example: Identifying sensitive nets • The board has been scanned with four different probe polarization (up, down, left, right) to take account of the induced current on the board • The medium size magnetic field probe was used with 1.5mm x 1.5mm scan resolution • ESD sensitive net can be identified roughly, but the resolution is not so fine enough to pin point a single trace. # 38

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