Design Issues of Flash-based SSD& Hybrid Disks

Design Issues of Flash-based SSD& Hybrid Disks Han-Lin Li Dept. Computer Science and Information Engineering National Taiwan University Advisor: Prof. Chia-Lin Yang 1

Outline Background NAND vs. NOR Organization and characteristics of NAND flash memory Trend of NAND flash memory technology Design Issues of Flash-Based SSD FTL design Efficient garbage collection Wear-leveling techniques Multi-Chip (bank) flash memory Flash memory as a swap device of virtual memory Design Issues of Hybrid Disk Our current work 2

Multi-Chip(bank) Flash Memory Use stripping and interleaving techniques to improve performance (RTAS’02) Bank 1 Sub-request Request 1 Sub- request Bank 2 Stripping example Bank 1 Request 2 Request 1 Bank 2 Interleaving example 3

Flash memory as a Swap Device of Virtual Memory • Replacement policy design (CASES’06, CODES+ISSS’06) • Subpaging (ISLPED’06) • HotCache (ISLPED’06) • Duplication-Aware Garbage Collection (TVLSI’08)

Clean-First LRU • The cost of swapping out a dirty page is much higher than swapping out a clean page • Splits the LRU list into • Working region • Clean-first region • Selects a clean page to evict in the clean-first region first to save flash write cost

OneNAND XIP • To reduce # of page faults • On page fault • Only load frequently used code page to main memory • Infrequently used code page use eXecution In Place (XIP) • How to identify frequently used code page? • If # of occurrences of the missed page in the page history window > a predefined threshold • Frequency used code page

Subpaging • Divide a virtual memory page into a set of subpages in the granularity of flash page size • Each subpage is associated with a dirty bit. Memory Page Flash Page Size 0 Clean Data Flash Memory One Write to Flash 1 Dirty Data Clean Data 0 0 Clean Data Dirty Bit

HotCache • Caching writes only • Preserving intra-page locality • Capturing hot data address translation table HotCache Management Physical address (f/s, bank, block, page) LBA 0 (f, 0, 0, 3) Garbage Collection … … 1 (f, 0, 1, 2) FTL layer 2 (s, -, 2, -) MTD layer Command translation Physical device HotCache Flash Memory

What is Intra-page Locality? • Flash pages in one main memory page are written to flash memory back to back Main memory D C D B Block X Block Y C D A0 B C Swap_out(A) D A1 B C A0 A1 A2 A3 C0 C1 C2 C3 D A2 B Virtual page C A4 A5 A6 A7 C4 C5 C6 C7 D A3 B C B0 B1 B2 B3 D0 D1 D2 D3 A0, A1, A2, A3, A4, A5, A6, A7 D A4 B C B4 B5 B6 B7 D4 D5 D6 D7 D A5 B C A6 B A7

Why is Preserving Intra-Page Locality Important? • It affects the efficiency of garbage collection Block X Block Y Block X Block Y After page A, B are swapped out A A A A C C C C C C C C A A A A C C C C C C C C B B B B D D D D D D D D B B B B D D D D D D D D Block X Block X Block Y Block Y A A A A B B B B C C C C D D D D C C C C D D D D C C C C D D D D C C C C D D D D B B B B A A A A

1 1 D D 1 0 B B D D B B D D B B D D B B Duplication-Aware Garbage Collection • Exploit data redundancy between the main memory and flash memory to eliminate unnecessary live page copying during garbage collection Main Memory Main Memory Dirty Bit Dirty Bit 1 1 D D D D 0 1 D D A A D D A Duplication-Aware Garbage Collection A A A A A Flash Memory Flash Memory A A A A C C C C B B B B C C C C An invalided page A free page

Design Issues of Hybrid Disk • Using NAND flash as disk cache • Issues • Saving power • Improving performance • Improving endurance

Prefetching Disk access address Caching Write buffering The energy consumption parameters for the Hitachi-DK23DA hard disk. time Disk idle time Saving Disk Power by Flash Cache • Disk is a big energy consumer in mobile systems • Can we reduce disk power? • If the disk is idle, we can change it to power saving mode • But the disk idle time may be less than the break even time • Could we extend the disk idle time? • Caching could reduce disk access • Prefetching can move disk access time forward • Write buffering can move disk access time backward

Our Current Works • Improve endurance through bit inversion • Improve performance through parallel garbage collection in a multi-bank flash system

Improving Endurance • Probability to damage a flash cell should be proportional to # of charge loss/gain in floating gates • Only writing 0 or erasing a cell containing 0 will charge/discharge a floating gate • We may reduce # of “0” writes to improve flash life time Tunnel Oxide Control Gate Stored electrons Floating Gate Substrate Drain Source Erased = “1” Programmed = “0”

Bit Inversion • If more than ½ bits in an inversion unit = 0 • Invert all bits in the inversion unit • Set flag = 1 • Advantage • Reduce # of 0 writes • Disadvantage • Additional bit write & space requirement • Additional write is negligible (<0.1%) • Put flag in spare area 5*“0” 3*”1” 3*“0” 5*”1” Inversion Unit Original data 1 0 0 0 0 1 0 1 0 0 1 1 1 0 1 1 Inverted data 0 1 1 1 1 0 1 0 1 0 0 1 1 1 0 1 1 0 Flag

Host Interface “0” Counter Bit Inversion • When data are written to flash • Data will be stored in SRAM temporarily • “0” counter count # of “0” in each inversion unit • Data will be written to flash latter after “write allocate” • If # of “0” in an inversion unit > threshold, • Invert all bits in the inversion unit • Set flag of the inversion unit = 1 • When data are read from flash • Read data from flash to SRAM • If the flag of an inversion unit = 1 • Invert all bits in the inversion unit Flash Memory Controller Host Interface CPU Core System Bus Inversion Logic Flash Interface SRAM Flash Memory Bus Flash Memory Chips

# of 0 in different unit size in files Test case 2 : a JPEG file Test case 1 : a MS word file 2KB 512B • Smaller inversion unit size => larger opportunity to reduce # of “0” writes

Parallel Garbage Collection • Parallel live page copying to improve performance • Copy live pages to different bank/chip Chip 1 Read live page1 Write live page1 Erase the block Chip 1 Read live page1 Erase the block Chip 2 Write live page1 Buffer Buffer Read live data Write live data Read live data Write live data Flash blocks Erase the block Erase the block Victim block Flash Chips Flash Chips

Reference • Park, S., Jung, D., Kang, J., Kim, J., and Lee, J. 2006. CFLRU: a replacement algorithm for flash memory. In Proceedings of the 2006 international Conference on Compilers, Architecture and Synthesis For Embedded Systems (Seoul, Korea, October 22 - 25, 2006). CASES '06. ACM, New York, NY, 234-241 • Energy-Aware Flash Memory Management in Virtual Memory System,L.-H. Lin, C.-L. Yang, H.-W., Tseng, to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems • An adaptive striping architecture for flash memory storage systems of embedded systems, L.-P. Chang and T.-W. Kuo, RTAS’ 02 • Joo, Y., Choi, Y., Park, C., Chung, S. W., Chung, E., and Chang, N. 2006. Demand paging for OneNAND™ Flash eXecute-in-place. In Proceedings of the 4th international Conference on Hardware/Software Codesign and System Synthesis (Seoul, Korea, October 22 - 25, 2006). CODES+ISSS '06. ACM, New York, NY, 229-234. • An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage, H.-W. Tseng, H.-L. Li, and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006 • Chen, F., Jiang, S., and Zhang, X. 2006. SmartSaver: turning flash drive into a disk energy saver for mobile computers. In Proceedings of the 2006 international Symposium on Low Power Electronics and Design (Tegernsee, Bavaria, Germany, October 04 - 06, 2006). ISLPED '06. ACM, New York, NY, 412-417.

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Design Issues of Flash-based SSD& Hybrid Disks