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CALICE Status

This update highlights the current status of the CALICE collaboration's study on calorimetry for a linear collider. The collaboration involves 150 people from 24 institutes across 8 countries and is expanding. The beam tests for the electromagnetic and hadronic calorimeters have been a major focus, with ongoing simulation studies and comparison work using Geant3/Geant4 for electron, pion, and proton responses. Progress has been made on the electronics design and testing as part of the project's development. For more details, visit the CALICE-UK page.

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CALICE Status

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  1. CALICE Status Paul Dauncey Imperial College London For the CALICE-UK groups: Birmingham, Cambridge, Imperial, Manchester, RAL, UCL Paul Dauncey - Calice Status

  2. The CALICE collaboration Study calorimetry for a future linear collider • Both electromagnetic (ECAL) and hadronic (HCAL) • ECAL studies are for Si-W tracking calorimeter • HCAL studies are for analogue scintillating tile or digital (small cell) made with RPC’s, scintillating tiles or GEM’s • Big collaboration already… • 150 people, 24 institutes, 8 countries (including Europe, US and Asia) • DESY is a member (CALICE grew out of TESLA TDR studies) • …and still expanding • 6 institutes have joined since the last LCUK meeting • FNAL have also approached the collaboration • Informal agreement on collaboration with SLAC/Oregon • Recent summary of status written for DESY PRC in October • Can find from CALICE-UK page http://www.hep.ph.imperial.ac.uk/calice/ Paul Dauncey - Calice Status

  3. CALICE beam test Major aim is beam test • ECAL 202020cm3 • 30 layers of tungsten • 9720 Si diode pads with analogue readout • HCAL 111m3 • 38 layers of iron • 15000 55cm2 scintillator pads with analogue readout, OR • 350000 11cm2 RPC, scintillator or GEM pads with digital readout • Timescale is short • mid 2004 – mid 2005 Paul Dauncey - Calice Status

  4. CALICE-UK approval UK project (finally!) approved in Dec 2002 • Funding only for two full FY’s, not the three requested • Funds up to March 2005; cannot complete beam test or do analysis! • Can reapply to extend in ~18 months • Equipment fund sufficient to build ECAL electronics • We will design and build VME boards and DAQ system for beam test • Hope to use same boards for HCAL readout (analogue and digital) • Full effort request granted for engineering from Rutherford Laboratory • New engineer (Adam Baird, RAL) has now joined the project • One RA post for two years at Cambridge • For simulation work, the other part of the UK involvement • Travel money for the two FY’s Paul Dauncey - Calice Status

  5. CALICE-UK simulation studies Two sets of studies going on • Jet resolution is major driver for fine-grained calorimetry • Simulation indicates required 30%/E is achievable using energy flow… • …but simulation needs to be verified • Hadronic interactions known to be difficult to model • Compare Geant3/Geant4/Fluka predictions • Birmingham and Cambridge groups • Beam energy spread will be significant • Luminosity will need to be known as a function of s • Bhabha rate is high and (obviously) depends directly on luminosity • Measure s for each event from acollinearity angle of e+ and e– • Could use tracker only but need very high efficiency at low angles • UCL group Paul Dauncey - Calice Status

  6. Geant3/Geant4 electron comparisons Expect EM response to be modelled well • Use beam test configuration for studies • Direct comparison to data when available • Agreement is reasonable after tuning • Low energy cut-offs • Production of -rays Paul Dauncey - Calice Status

  7. Geant3/Geant4 pion comparisons Did not expect hadronic response to be as good • Pion beam agreement also pretty reasonable after same tuning • Comparable to (better than?) electrons Paul Dauncey - Calice Status

  8. Geant3/Geant4 proton comparisons Protons show much worse agreement • Small nucleon component in all jets • Causes almost all of small discrepancy in pion jets • Importance of using proton test beam • Not previously recognised Data may be different from both models! Paul Dauncey - Calice Status

  9. CALICE-UK electronics work • Effort from several groups in ECAL readout electronics • Imperial, Manchester, UCL • Following approval, RAL TD became involved; brought experience of CMS tracker • Significant knowledge of design of Front End Driver (FED) • Readout board for CMS silicon tracker • Around 500 boards needed for whole tracking system • FED architecture close to proposed CALICE board • Data gathering and control almost identical • Actual data input technology very different; CMS use fibre • FED design is quite advanced • Physical board layout complete, firmware designs in progress • Two “final-specification” prototypes received two weeks ago and currently undergoing tests Will now use FED as a starting point for CALICE Paul Dauncey - Calice Status

  10. Original proposed system Readout board most complex part • Each cable handled by slave FPGA • Whole board controlled by master FPGA 15 readout boards • Each handles digitisation of 2 layers 1 trigger board • Holds off further triggers until readout complete 1 test board (not shown) • For testing cable connections of readout board Paul Dauncey - Calice Status

  11. 5V 3.3V Run/Halt Config E2PROM Id E2 Prom 1.5V 0V 3.3V Compact Flash 1 5V 3.3V 1.5V 1 Test Connector 1 VME LEDs 4x Prog Delay 1 Dual ADC 12x Opto Rx 1 Power Good PD Array VME64x Interface FPGA FPGA Synch & Processing Boundary Scan System ACE Buffer Jumper Matrix -5V ASIC Vref 12x trim dac VME FE 1 3 6 4x Prog Delay +12V 12 Dual ADC LEDs +5V Temp Sense Front End FPGA +3.3V FPGA Temp Sense Clock Control Data 2.5V 1.5V +2.5V 0V LEDs 2 +1.5V QDR SSRAM -5.0V spare Over temp LEDs TTS TTCrx TTC DAQ ASIC Readout & Synch Control FLT LEDs EMU FSYNC Spare Process Back End FPGA LEDs Transfer VME Temp Sense 43 85 Clock Control Data 22 Readout 4x Prog Delay 3.3V 1.5V Dual ADC 8 Busy 12x Opto Rx 8 LEDs error PD Array FPGA halted Synch & Processing 12x trim dac ASIC Vref FE 8 Master  BE +VME; very similar 24 4x Prog Delay 5.0 V 48 96 E-Fuse Hot swap DC-DC 3.3 V Dual ADC Front End FPGA FPGA 2.5V PD Temp Sense Slave  FE; need to rewrite firmware 1.5V -5.0V extract ADCs, etc; totally different Hot swap cycle SW Live extract request SW FED board compared to readout board Paul Dauncey - Calice Status

  12. FED layout • Ideally • Keep everything to the right • Redo everything to the left • FED is bigger • More £ per board • More channels per board also • Total cost approximately the same • Saving is on schedule and effort Paul Dauncey - Calice Status

  13. ECAL electronics schedule 2003 2004 Paul Dauncey - Calice Status

  14. CALICE summary • CALICE as a whole is still growing • Dominating the LC calorimetry community • CALICE-UK is finally approved • Not everything we wanted (yet) • Will keep us going for the next two years • Simulation studies producing useful results • Indicating the importance of proton beams • Ensures beam test will be sensitive to most critical issues • Electronics getting close to producing hardware • Now based on CMS FED board; cost neutral but less effort needed • Should have prototypes this summer, final boards early in 2004 Paul Dauncey - Calice Status

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