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Logic Design: Demultiplexers, Decoders, and Realization of Logic Functions using Decoders

Learn about demultiplexers & decoders in digital logic design, including constructing, connecting, & using gates. Realize logic functions using decoders with examples. End of Lecture 25.

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Logic Design: Demultiplexers, Decoders, and Realization of Logic Functions using Decoders

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  1. Lecture 25: Logic Design (Part 2) PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

  2. De-Multiplexers • A demultiplexer is an electronic switch that works in a reverse manner as compared to a multiplexer: • A set of n output lines D = {D0, D1, …, Dn-1} • A set of m select input lines S = {S0, S1, …, Sm-1} • One data input line IN • The input data line will be connected to one of the outputs depending upon the value of the select lines (D0 = IN if S = 0, D1 = IN if S = 1, D2 = IN if S = 2, and so on). • The outputs that are not selected are set to 0. • Usually, n = 2m. • Also called a 1-to-2mdemultiplexer.

  3. 1-to-2m DEMUX D0 D1 IN Dn-1 S0 S1 Sm-1

  4. MUX-DEMUX for Data Communication

  5. Implement a 1-to-2 DEMUX using Gates D0 1-to-2 DEMUX IN D1 S0 D0 = S0’.IN D1 = S0.IN

  6. Implement a 1-to-4 DEMUX using Gates 1-to-2 DEMUX D0 D1 IN D2 D3 S1 S0 D0 = S1’.S0’.IN D1 = S1’.S0.IN D2 = S1.S0’.IN D3 = S1.S0.IN

  7. Decoder • A decoder can be considered as a special case of a demultiplexer. • A DEMUX with the data input IN always set to 1. • It has n inputs and 2n outputs (typically). • Depending on the applied input, exactly one of the output lines is set to 1, while all the other lines are set to 0. • In some decoder, the reverse convention is also followed – the selected output line is set to 0, while all others are set to 1. • Many applications: • Selecting one out of many functional blocks (e.g. memory). • Code conversion, data distribution, etc.

  8. Example: A 2-to-4 decoder 2-to-4 decoder f0 D0 f1 f2 D1 f3 f0 = D1’.D0’ f1 = D1’.D0 f2 = D1.D0’ f3 = D1.D0

  9. A decoder typically has an enable input G. • If G = 0, the decoder is enabled; if G = 1, all the outputs are deactivated. 2-to-4 decoder f0 D0 f1 f2 D1 f3 G f0 = D1’.D0’.G’ f1 = D1’.D0.G’ f2 = D1.D0’.G’ f3 = D1.D0.G’

  10. Constructing 4-to-16 Decoder using 2-to-4 Decoders • Four inputs D0, D1, D2 and D3, and 16 outputs f0, f1, …, f15. • We require five 2-to-4 decoders. • Four decoders to generate the 16 outputs. • One decoder to select one of the four decoders.

  11. Constructing a 4-to-16 Decoder using 2-to-4 Decoders f8 f0 f4 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder f1 f9 f5 f2 f6 f10 f11 f3 f7 f12 2-to-4 decoder f13 f14 f15

  12. Realizing Logic Functions using Decoder • We can use an n-to-2ndecoder and an OR gate to realize any function of n variables. • The n input variables are connected to the decoder inputs. • All the outputs corresponding to the true minterms are fed to the inputs of the OR gate. • The OR gate output generates the function. • We shall be illustrating the process with an example.

  13. END OF LECTURE 25

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