Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs

1. Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs Mohammad Taherzadeh-Sani and Anas A. Hamoui IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 9, SEPTEMBER 2006 Page(s):966-970 指導教授：易昶霈 學　　生：吳柏翰 　學　　號：97662002

2. Outline • Introduction • Digital Calibration Technique • Simulation Results • Appendix

3. Introduction (1/3) • The linearity of a pipelined analog-to-digital converter (ADC) is primarily degraded by the linearity errors in its pipeline stages. • The gain errors in the residue amplifier, due to the finite gain and dynamic effects of its operational amplifier. • The nonlinearity in the digital-to-analog subconverter (sub-DAC), due to capacitor-mismatch errors.

4. Introduction (2/3)

5. Introduction (3/3) • The proposed technique randomly swaps the feedback capacitor with the sampling capacitor(s) in the multiplying DAC (MDAC) of each pipeline stage. • Both the measurement and calibration of the capacitor-mismatch errors in each pipeline stage are then performed entirely digitally, using simple logic circuits.

6. Digital Calibration Technique (1/6) • Digital Calibration of 1-bit Pipeline Stages :

7. Digital Calibration Technique (2/6)

8. Digital Calibration Technique (3/6)

9. Digital Calibration Technique (4/6) • Effect of gain error on capacitor-mismatch calibration:

10. Digital Calibration Technique (5/6) • Fully differential MDAC:

11. Digital Calibration Technique (6/6) • Digital Calibration of Multibit Pipeline Stages :

12. Simulation Results (1/2) • SNDR : signal-to-noise-and-distortion ratio. • SFDR : spurious-free dynamic range.

13. Simulation Results (2/2)

14. The end.Thank you for your listen.

15. Appendix (1/3)

16. Appendix (2/3)

17. Appendix (3/3)