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Performance of Programmable Logic Devices (PLDs) in read-out of high speed detectors

Performance of Programmable Logic Devices (PLDs) in read-out of high speed detectors. Jack Fried INSTRUMENTATION DIVISION. PLD ? Muon Tracker PLD. What Is a PLD. PLD Building Blocks. Logic Block. Device Features. PLD Features (cont). I/O Protocols. Design Entry. Plug In Manager.

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Performance of Programmable Logic Devices (PLDs) in read-out of high speed detectors

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  1. Performance of Programmable Logic Devices (PLDs) in read-out of high speed detectors Jack Fried INSTRUMENTATION DIVISION • PLD ? • Muon Tracker PLD

  2. What Is a PLD

  3. PLD Building Blocks

  4. Logic Block

  5. Device Features

  6. PLD Features(cont)

  7. I/O Protocols

  8. Design Entry

  9. Plug In Manager

  10. Mega Functions

  11. Design Verification • Simulation • Built in real time Logic analyzer

  12. PLD Design Flow

  13. PHENIX Muon Tracker

  14. Muon Tracker Crate

  15. Cathodes Read-Out Card (CROC) • Design Requirements • 64 Channel Readout per CROC • Less than 3125 electrons (RMS) noise for 10-150 pF of detector capacitance (including 24” cable) • • Less than 1% crosstalk between any channels on the board • gain: 3.5mV/fC • Digital/Analog isolation • Main Components • AMU-ADC • CPA digital Analog Signal

  16. Controller Card (CNTL) • Design Requirements • Control AMU/ADC data collection, conversion and read-out • Provide connection to 2 CROC boards • Provide connection to the outside world • Support the T&FC and DCM interface • Provide data relay from remote controller board to DCM • Support ARCnet connectivity to serial configuration bus • FPGA - the brain • developed by Jack • work in progress CNTL Card

  17. Muon Tracker Crate Block Diagram

  18. Requirements for Muon tracker PLD • Trigger rate 25Khz • 4 samples per pulse • Sample new data on every beam crossing • Holds 5 events • 100ns between triggers (burst rate) • Control digital part of AMUADC -RD-WR • Send data to DCM • Allow for Master and slave modes

  19. Muon TrackerPLD Programming Difficulties • Board already designed • PLD already chosen (FLEX10K50E) • Pins allocated • PLD to small • Overlapping events • AMUADC noise problems • AMUADC requires special RD WR sequence

  20. ALTERA10K50

  21. Memory Requirements • 4 samples per event • Need to be able to store 5 events • Each sample is 11bits • 32 channels per AMUADC • 4 AMUADC PER CNTL 128 channels 28160 BITS TOTAL

  22. Memory Implementation • Used 9 EABs • Only 1 EAB left for PLD algorithm • Lost 8704 bits

  23. AMUADC cellWriting & Reading

  24. Overlapping Events

  25. MUON TRACKERPLD

  26. MUON TRACKERPLD

  27. AMU Cell Manager

  28. AMUADC Controller

  29. Read Out Managerpart1

  30. Read Out Managerpart2

  31. Read Out ManagerPart3

  32. DCM Output Manager

  33. Compilation Result

  34. Current code

  35. Muon FEE • PLD - current code • store every beam crossing • 4-sample per pulse • readout time 53uS • hold 4 events Time

  36. END

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