EE434 ASIC & Digital Systems

1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

2. Lecture 10 FPGA fabric architecture concepts Reference: Chapter 3 of the text book

3. Programmable Interconnect • Interconnect Network • Flexibility • Routing bottleneck should be avoided • Interconnect delay needs to be considered • Area/performance/power tradeoff • Global and cell-to-cell wiring

4. D Q Programmable interconnect • MOS switch controlled by configuration bit:

5. Array-Based Programmable Wiring Interconnect Point Programmed interconnection Input/output pin Cell Horizontal tracks Vertical tracks

6. Programmable vs. fixed interconnect • Switch adds delay. • Transistor off-state is worse in advanced technologies. • FPGA interconnect has extra length => added capacitance

7. Interconnect strategies • Some wires will not be utilized. • Congestion will not be same throughout the chip. • Types of wires: • Short wires: local LE connections • Global wires: long-distance, buffered communication • Special wires: clocks, etc.

8. Paths in interconnect • Connection may be long, complex. LE LE LE LE LE Wiring channel LE LE LE LE LE Wiring channel LE LE LE LE LE

9. XC4000 Interconnect

10. Interconnect architecture • Connections from wiring channels to LEs. • Connections between wires in the wiring channels. Wiring channel LE LE

11. Switchbox channel channel channel channel

12. Mesh-based Interconnect Network Switch Box Routing of the data Connect Box Connects cell I/Os To the global interconnect InterconnectPoint Courtesy Dehon and Wawrzyniek

13. Transistor Implementation of Mesh Courtesy Dehon and Wawrzyniek

14. Spartan-II interconnect • Types of interconnect • local • general-purpose • dedicated • I/O pin

15. Spartan-II general-purpose network • Provides majority of routing resources • General routing matrix (GRM) connects horizontal/vertical channels and CLBs. • 24 single-length lines to connect each GRM to four nearest GRMs • Hex lines connect GRM to GRMs six blocks away. • 12 long lines span the chip.

16. Spartan-II routing • Relationship between GRM, hex lines, and local interconnect

17. Spartan-II three-state bus • Horizontal on-chip busses:

18. Altera MAX From Smith97

19. t PIA LAB1 LAB2 PIA t PIA LAB6 Altera MAX Interconnect Architecture column channel row channel LAB Array-based (MAX 3000-7000) Mesh-based (MAX 9000) Courtesy Altera

20. Antifuse • Permanently programmed • Make a connection with electrical signal • More reliable than breaking a connection • Resistance of about 100 W

21. Flash-programmed FPGA • Flash is electrically-erasable EPROM • Allows reprogramming without boot-up procedure

22. Logic blocks • The logic blocks in antifuse-programmed FPGAs are generally based on multiplexing. • Program by making/breaking connections a out 0 d0 1 d1 d0 out d1 a Truth table

23. 0 0 1 1 0 0 0 0 Larger logic block

24. Actel 54SX logic element (C cell)

25. Uses two C-cells in Super Cluster Adds bits A0 and A1 Carry in FCI, carry out FCO Active when CFN is high Actel 54SX adder logic

26. Actel 54SX R cell

27. Actel 54SX LE • C/R cells organized into clusters • Type 1 cluster: CRC • Type 2 cluster: CRR • Clusters grouped into super clusters • Type 1: two type 1 clusters • Type 2: one type 1, one type 2

28. RAM-based FPGA Xilinx XC4000ex • 1000 CLBs • 32 x 32 Array • 25,000 gates • 422 kbits of RAM • Clock speed 20-50 MHz Courtesy Xilinx

29. A Low-Energy FPGA (UC Berkeley) • Array Size: 8x8 (2 x 4 LUT) • Power Supply: 1.5V & 0.8V • Configuration: Mapped as RAM • Toggle Frequency: 125MHz • Area: 3mm x 3mm

30. Larger Granularity FPGAs PADDI-2 (UC Berkeley) • 0.8 um2-metal CMOS tech • 11.5 x 11.5 mm2 • 600k transistors • 208-pin PGA • fclock = 50 MHz • Pav= 3.6 W @ 5V • Basic Module: Datapath

31. RAM 500 k Gates FPGA + 1 Gbit DRAM Preprocessing Multi- Spectral Imager Analog 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS mC system +2 Gbit DRAM Design at crossroads: System-on-a-Chip • Embedded applications where cost,performance, and energy are the real issues! • DSP and control intensive • Mixed-mode • Combines programmable and application-specific modules • Software plays crucial role

32. Addressing the Design Complexity IssueArchitecture Reuse Reuse comes in generations Source: Theo Claasen (Philips) – DAC 00

33. Addressing the Design Complexity IssueArchitecture Reuse Reuse comes in generations

34. Architecture Reuse • Silicon System Platform • Flexible architecture for hardware and software • Specific (programmable) components • Network architecture • Software modules • Rules and guidelines for design of HW and SW • Computer Processors • Dominance of a few players who specify and control architecture • Application-domain specific (difference in constraints) • Speed (compute power) • Power dissipation • Costs • Real / non-real time data

35. Platform-Based Design “Only the consumer gets freedom of choice; designers need freedomfromchoice” (Orfali, et al, 1996, p.522) • A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer. • New platforms will be defined at the architecture-micro-architecture boundary. • They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations. • Key to such approaches is the representation of communication in the platform model. Source:R.Newton

36. FPGA Reconfigurable Data-path Interface ARM8 Core Berkeley Pleiades Processor • 0.25um 6-level metal CMOS • 5.2mm x 6.7mm • 1.2 million transistors • 40 MHz at 1V • 2 extra supplies: 0.4V, 1.5V • 1.5~2 mW power dissipation

37. Heterogeneous Programmable Platforms FPGA Fabric Embedded memories Embedded PowerPc Hardwired multipliers Xilinx Vertex-II Pro High-speed I/O Courtesy Xilinx