Mentor Graphics Simulation Tools for ASIC Design

1. Mentor Graphics Simulation Tools for ASIC Design Victor P. Nelson

2. ASIC Design Flow Simulation Behavioral Model VHDL/Verilog Verify Behavior Synthesis DFT/BIST & ATPG Gate-Level Netlist Verify Function Full-custom IC Test vectors Transistor-Level Netlist Verify Function & Timing Standard Cell IC & FPGA/CPLD DRC & LVS Verification Physical Layout Map/Place/Route Verify Function & Timing IC Mask Data

3. ADVance MSDigital, Analog, Mixed-Signal Simulation VHDL,Verilog, VHDL-AMS, Verilog-A, SPICE Netlists VITAL SPICE models Design_1 Design_2 IEEE 1164 Working Library Resource Libraries ADVance MS Input Stimuli Simulation Setup Mixed Signal (VHDL-AMS, Verilog-A) EZwave or Xelga Eldo, Eldo RF ModelSim Analog (SPICE) Mach TA Mach PA View Results Digital (VHDL,Verilog)

4. Mentor Graphics Legacy Simulators • Originally designed for PCB design • Quicksim II : digital, gate-level simulation • Invoke : quicksim • ASIC Design Kit : adk_quicksim • Xilinx FPGA : pld_quicksim, Altera : max2_quicksim • Quicksim Pro : mixed schematic & HDL • Uses both Quicksim II and Modelsim EE • Invoke: qspro • Accusim : analog simulation (SPICE) • Invoke : adk_accusim

5. Basic simulation environment • -Behavioral description, • -Circuit structure/netlist, • -Timing information, etc. Behavior/ • -Digital values, • -Analog voltages/ • currents, • -Waveforms -Generic, -Technology- specific • Results listings, graphical waveforms, • Reports of measurements, result checks, • constraint violations, etc.

6. Mentor Graphics ASIC Design Kit (ADK) • ASIC technology files & standard cell libraries • AMI: ami12, ami05 (1.2, 0.5 μm) • TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm) • IC flow & DFT tool support files: • Simulation • VHDL/Verilog/Mixed-Signal models(Modelsim/ADVance MS) • Analog (SPICE) models(Eldo/Accusim) • Post-layout verification (Mach TA) • Digital schematic (Quicksim II, Quicksim Pro)(exc. tsmc025,tsmc018) • Synthesis library of std. cells (LeonardoSpectrum) • Design for test & ATPG (DFT Advisor, Flextest/Fastscan) • Schematic capture (Design Architect-IC) • IC physical design (standard cell & custom) • Floorplan, place & route (IC Station) • Design rule check, layout vs schematic, parameter extraction (Calibre)

7. HDLs in Digital System Design • Model and document digital systems • Hierarchical models • System, RTL (Register Transfer Level), gates • Different levels of abstraction • Behavior, structure • Verify circuit/system design via simulation • Modelsim EE (VHDL, Verilog, System C) • ADVance MS (above + VHDL-AMS, Verilog-A) • Synthesize circuits from HDL models • Leonardo (Synopsis)

8. -- count4.vhd 4-bit parallel-load synchronous counter LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY count4 IS PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); END count4; ARCHITECTURE rtl OF count4 IS SIGNAL int : unsigned(3 downto 0); BEGIN PROCESS(clear, clock, enable) BEGIN IF (clear = '1') THEN int <= "0000"; ELSIF (clock'EVENT AND clock='1') THEN IF (enable = '1') THEN IF (load_count = '1') THEN int <= D; ELSE int <= int + "01"; END IF; END IF; END IF; END PROCESS; Q <= int; END rtl; Typical VHDL behavioral model

9. Test stimulus:Modelsim “do” file: count4_rtl.do add wave /clock /clear /enable /load_count /D /Q add list /clock /clear /enable /load_count /D /Q force /clock 0 0, 1 10 -repeat 20 force /clear 0 0, 1 5, 0 10 force /enable 0 0, 1 25 force /load_count 0 0, 1 20, 0 35, 1 330, 0 350 force /D 10#5 0, 10#9 300 run 400

10. Testbench: count4_bench.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY count4_bench is end count4_bench; ARCHITECTURE test of count4_bench is component count4 PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); end component; for all: count4 use entity work.count4(behavior); signal clk : STD_LOGIC := '0'; signal clr, en, ld: STD_LOGIC; signal din, qout: unsigned(3 downto 0); begin C4: count4 port map(clk,clr,en,ld,din,qout); clk <= not clk after 10 ns; P1: process begin din <= "0101"; clr <= '1'; en <= '1'; ld <= '1'; wait for 10 ns; clr <= '0'; wait for 20 ns; ld <= '0'; wait for 200 ns; end process; end; Alternative to “do” file Could check results & “assert” error messages

11. Count4 – Simulation waveform Clear Counting Parallel Load

12. ADVance MS : mixed-signal simulation A/D converter digital analog VHDL-AMS

13. VHDL-AMS models D/A converter Comparator

14. ADVance MS: mixed Verilog-SPICE Verilog top (test bench) SPICE subcircuit

15. Leonardo synthesis procedure • Invoke leonardo • Select & load a technology library (ASIC or FPGA) • ASIC > ADK > TSMC 0.35 micron • Read input VHDL/Verilog file(s): count4.vhd • Enter any constraints (clock freq, delays, etc.) • Optimize for area/delay/effort level • Write output file(s) • count4_0.vhd - VHDL netlist (for simulation) • count4.v - Verilog netlist (for IC layout) • count4.sdf - Standard delay format file (for timing) • count4.edf - EDIF netlist (for Xilinx/Altera FPGA)

16. Leonardo-synthesized netlist count4_0.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; library adk; use adk.adk_components.all; -- ADDED BY VPN entity count4 is port ( clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ; D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ; end count4 ; architecturenetlistof count4 is signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189: std_logic ; begin Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ; Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear); ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable ); ix9 : oai21 port map ( Y=>nx8, A0=>load_count, A1=>Q_0_EXMPLR, B0=>nx169 ); ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count); Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear); ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> enable); ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count, B0=>nx14, B1=> nx22); ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR); ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> load_count); Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> enable); ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189); ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR); ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187); ix186 : inv01 port map ( Y=>nx185, A=>load_count); ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR); ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count); Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> enable); ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>load_count); ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187); end netlist ;

17. Post-synthesis simulation(Leonardo-generated netlist) • Verify synthesized netlist matches behavioral model • Create simulation primitives library for std cells: >vlib adk >vcom $ADK/technology/adk.vhd >vcom $ADK/technology/adk_comp.vhd • Insert library/package declaration into netlist library adk; use adk.adk_components.all; • Simulate in Modelsim, using “do file” or test bench from original behavioral simulation • results should match models of all ADK std cells

18. Preparation for Layout • Convert Verilog netlist to Mentor Graphics “EDDM” schematic/netlist format • Invoke Design Architect-IC (adk_daic) • On menu bar, select File > Import Verilog • Netlist file: count4.v (the Verilog netlist) • Output directory: count4(for the EDDM netlist) • Mapping file $ADK/technology/adk_map.vmp • Open the schematic for viewing • Click Schematic in DA-IC palette • Select schematic in directory named above (see next slide) • Click Update LVS in the schematic palette to create a netlist to be used later by “Calibre” • Create design viewpoints for ICstation tools • adk_dve count4 –t tsmc035 (V.P’s: layout, lvs, sdl, tsmc035) • Can also draw gate/transistor schematics directly in DA-IC using components from the ADK library

19. “count4” schematic (from Leonardo-generated netlist)

20. Simulating the schematic model • Quicksim II(legacy – “Falcon Framework”) • EDDM netlist models • create in Design Architect/Design Architect-IC • component models • Stimulus in “do file”, similar to Modelsim • Eldo – analog/SPICE simulator • Accusim – legacy analog/SPICE simulator • Export VHDL/Verilog netlist for HDL simulator

21. Mentor Graphics “Falcon” Framework Tools

22. Preparation for using Quicksim IICreate netlist & design viewpoints • “Design viewpoint” provides downstream tools with tool-specific information • primitives, properties, parameters • technology-specific simulation models • Create viewpoints one time for each schematic adk_dve design –technology tsmc035 • design = schematic netlist component name • tsmc035 = ASIC technology to be used • ASIC technologies available in ADK: tsmc018**, tsmc025**, tsmc035, ami05, ami12 (** no Quicksim models)

23. Design viewpoints for component “bob” Logic symbol ICgraph Layout viewpoint Layout vs. schematic check viewpoint Accusim viewpoint Schematic Back annotation file for layout parameter extraction Schematic-driven layout viewpoint (ICgraph) Transistor-level Quicksim II viewpoint Mentor Graphics “Design Manager”

24. Quicksim II operation • Invoke Quicksim II: adk_quicksim bob/tsmc035 • “bob” = design component • “tsmc035” = quicksim viewpoint • Quicksim II “kernel” has three modes: • Unit (default): all components have 1 unit of delay • Delay: delays specified as “triplets” • (min-delay typ-delay max-delay) • from technology files • Constraint: same as Delay, but with detection of glitches, contraint violations, etc.

25. Quicksim II multi-valued simulation • Each signal has a “state” and a drive “strength” Example: 1s = strongly driven to 1 1r = resistively pulled up to 1

26. Example “force file” for circuit “bob”(similar to Modelsim EE) force a 0 0 force a 1 25 force a 0 55 force r 1 0 force r 0 7 force r 1 12 set clock period 20 force c 0 0 -repeat force c 1 10 -repeat Value State Clock definition

27. Quicksim II simulation of “bob”

28. Eldo simulation from DA-IC • Run simulations from within DA-IC • Eldo, ADVance MS, Mach TA • DA-IC invokes a “netlister” to create a circuit model from the schematic • SPICE model for Eldo & Mach TA • Eldo analyses, forces, probes, etc. same as SPICE • View results in EZwave or Xelga

29. Eldo input and output files -Netlist -Simulation cmds -Stimulus

30. SPICE “circuit” file generated by DA-IC SPICE netlist for modulo7 counter From ADK library Force values (created interactively)

31. Eldo simulation of modulo7 counter(transient analysis)

32. Post-layout simulation with MachTA • MachTA is an accelerated Spice simulator • Digital & mixed-signal circuits • Analyze timing effects pre- and post-layout • SPICE netlists with parasitic R/C • Execute test vector file to verify functionality • Algorithms support large designs • Partition design, simulate only partitions with changes • Combine time-driven & event-driven operation • Solves linearized models using a proprietary high-performance, graph-theory based, matrix solution algorithm

33. Mach TA flow diagram SPICE netlist $ADK/technology/mta/tsmc035

34. Post-layout simulation with Mach TA(netlist extracted by Calibre PEX) • Prepare netlist (remove subcircuits for Mach TA) • Extracted netlist = count4.pex.netlist • Command: $ADK/bin/mta_prep count4 • Creates SPICE file: count4.sp • Invoke Mach TA: ana- command file to initialize Anacad SW mta –ezw –t $ADK/technology/mta/tsmc035 count4.sp • Mach PA (mpa) does current & power analysis

35. Mach TA main window

36. Mach TA simulation commands

37. Sample Mach TA “dofile”(transient analysis) Signals to observe in EZwave plot v(clk) v(q[2]) v(q[1]) v(q[0]) measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v l load l reset h count l clk run 5 ns h reset h clk run 5 ns l clk run 5 ns h clk run 5 ns Measure time from rising edge of clk (TRIGger) to 1st rising edge of q[0] (TARGet) - voltages Drive signals low/high (Lsim format) Simulate for 5 ns Command to execute: dofile file.do

38. EZwave waveform viewer(results for previous dofile) Double-click signal name to display.

39. Alternative Mach TA “dofile”(same result as previous example) plot v(clk) v(q[2]) v(q[1]) v(q[0]) measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n) l load l reset h count run 5 ns h reset run 200 ns v-levels delay rise fall width period Nodes to which source connected Periodic pulses Voltage source name

40. Mach TA – test vector file • Verify design functionality/behavior • apply test vectors • capture outputs • compare outputs to expected result • vectors/outputs from behavioral simulation • Command to execute a test vector file: run –tvend tvfile.tv test vector file (next slide)

41. Test vector file format # Test vector file for modulo7 counter CODEFILE UNITS ps RISE_TIME 50 FALL_TIME 50 INPUTS clk,reset,load,count,i[2],i[1],i[0]; OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max); CODING(ROM) RADIX <11113>3; @0 <01105>X; @2000 <00105>0; @7000 <01105>0; @10000 <11105>5; @20000 <01015>5; @30000 <11015>6; @40000 <01015>6; @50000 <11015>0; @60000 <01015>0; ….. END signal order within vectors Header Vector format Sample 5 fs before next vector Vectors: @time <input_vector>expected_output Test vectors derived from behavioral simulation results

42. Behavioral simulation listing Corresponding Mach TA test vector file

43. Alternate test vector file(clock generated separately by voltage source) vpulse vclk clk 0 pulse(0 3.3 10n .5n .5n 10n 20n) Can mix other simulation commands with test vector application.

44. Mach TA structure & schematic viewer

45. Summary • Simulation at each stage of ASIC design • behavioral model • synthesized netlist • pre-layout schematic/netlist • post-layout netlist • ADVance MS combines 3 technologies to cover the above • digital (VHDL, Verilog) • analog/mixed-signal (VHDL-AMS, Verilog-A) • transistor level (Eldo, Mach TA) • ASIC Design Kit (ADK) supports all tools in the design flow, including simulation