Carbon Nanotube Technology An Alternative in Future SRAM memories UPC

1. Carbon Nanotube Technology An Alternative in Future SRAM memories UPC CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

2. Introduction • In Si-bulk CMOS technology the variability of the device parameters is a key drawback and it may be a limiting factor for further miniaturizing nodes. • OBJECTIVE: to evaluate the variability in Carbon nanotube Field Effect Transistor (CNFET) as well as its real capability to be a promising alternative to Si-CMOS technology. Impact of carbon nanotube (CNT) diameter variations and the presence of metallic CNTs in the transistor (device level). Comparison between Si-CMOS and CNFET 6T SRAM cells (circuit level). CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

3. Device level Carbon Nanotubes (CNTs) Carbon nanotube Chiral vector angle of the atom arrangement along the tube Graphene Metallic Behaviour Diameter Semiconducting Rest of Rest of CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

4. Device level Carbon Nanotube Field Effect Transistors (CNFETs) An “Ideal” MOSFET-like CNFET is formed by 1 or more semiconducting CNTs perfectly aligned and well-positioned whose section under the gate is intrinsic and the s/d extension regions are n/p doped. Promising candidates to replace silicon CMOS due to its high performance There are some imperfections inherent to CNT synthesis and CNFET manufacturing process that may eclipse the expectations CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

5. Device level SOURCES OF VARIATION CNT growth process CNFET manufacturing process NO control of chirality • S/D doping variations • Mispositioned and misaligned CNTs • Percentage of m-CNTs • Diameter variations Semiconducting CNTs Metallic CNTs CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

6. Device level CNFET device model [1] [1] J. Deng and H.-S. Wong, “A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application part II: Full device model and circuit performance benchmarking,” Electron Devices, IEEE Transactions on, vol. 54, no. 12, pp. 3195–3205, 2007. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

7. Device level Monte Carlo experiment Example of IDS − VDS distribution for 50 CNFET samples. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

8. Device level STD (σ) of VTH and K Percentage of variation (100x3σ/μ) CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

9. Circuit level • Variability analysis and performance in CMOS and CNFET SRAM 6T cells CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

10. Circuit level • CNFET SRAM cell versus Si-MOSFET SRAM cell (nominal comparison) CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

11. Circuit level • CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison) CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

12. Circuit level • CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison) CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

13. Circuit level • CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison) CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

14. Device level • Conclusions • CNFETs are promising candidates to replace Si-MOSFETs due to their high current driving capability, tolerance to temperature and low leakage currents. • Manufacturing variability, that is one of the key limiting factors in silicon-MOS technology, has been investigated for such CNFET devices. • Considering a range of metallic tubes from 33% (current growth methods) to 0% (perfection) and a realistic distribution of diameters, it has been shown that the variability of both K factor and VTH is lower than CMOS for transistors with just 8 nanotubes, and much better for 12 tubes. • In a future scenario with a narrower distribution of CNT diameters, variation for both parameters could reach levels from 15% to 25%, fact that would allow a design procedure without the stress caused by variability in current conventional technology. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

15. Circuit level • Conclusions • CNFETs can be also considered as a potential alternative to CMOS in memory systems. • CNT technology presents better performance than CMOS technologies. However the implementation maturity of CNFET is still pending of several years of development. • Variability analysis shows as a promising prospect, that even for todays CNFETs performance, its variability is comparable with that of Si-MOS technology in a scenario which we have called ”moderated”. • Therefore, improvements in the control of chirality, the variability of CNFETs could be lower than in that moderated scenario. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

16. Thanks for your attention! CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

17. Device level Carbon Nanotubes (CNTs) Carbon nanotube Graphene Diameter & VTH CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

18. Device level Mean (μ) of VTH and K • Mean of Vth as Tm • Mean of Vth as N • Mean of K as Tm • Mean of K as N CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011