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Robustness of SRAM Memories Universitat Politecnica de Catalunya (UPC) Barcelona Spain

Robustness of SRAM Memories Universitat Politecnica de Catalunya (UPC) Barcelona Spain Ioana Vatajelu. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions. Overview

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Robustness of SRAM Memories Universitat Politecnica de Catalunya (UPC) Barcelona Spain

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  1. Robustness of SRAM Memories Universitat Politecnica de Catalunya (UPC) Barcelona Spain Ioana Vatajelu CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  2. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  3. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  4. Problem Statement Wafer to wafer Die to die Parametric Failures CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011 SRAM bit cell: • Minimum size transistors –> high sensitivity to process variability • Inter-die • Intra-die • Systematic • Random (RDF & LER) asymmetric transistors strengths

  5. Problem Statement CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  6. Problem Statement + 1 1 VDD GND + 0.8 0.8 Read Mode 0.6 Hold Mode Write Mode 0.6 1 0.4 0.8 0.4 0.2 0.6 0.2 0 0 0.4 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0.2 0 0 0.2 0.4 0.6 0.8 1 CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  7. Problem Statement Hold Mode Read Mode Access Write Mode FAIL FAIL FAIL FAIL 1.2 1.2 1.2 1.2 1 1 1 1 0.8 0.8 0.8 0.8 0.6 0.6 0.6 0.6 0.4 0.2 0.4 0.4 0.4 0 0.2 0.2 0.2 -0.2 0 0.5 1 1.5 0 0 0 -10 x 10 -0.2 -0.2 -0.2 0 2 4 6 8 0 0.5 1 1.5 0 0.5 1 1.5 -10 -10 -10 x 10 x 10 x 10 CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  8. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  9. The SB-SI Method Acceptance Region E.I. Vatajelu, J. Figueras, IEEE DATE 2011 Failure Region Statistical Distribution min mean p1 Acceptance Region Failure Region CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  10. The SB-SI Method E.I. Vatajelu, J. Figueras, IEEE DATE 2011 p2 Statistical Distribution p1 p2 p1 CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  11. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  12. Failure analysis of the 6T SRAM Static analysis - SNM CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  13. Failure analysis of the 6T SRAM Static analysis - SNM CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  14. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  15. ΔVTHNR Parametric Yield ΔVTHPL ΔVTHNR WL BL BLB PR PL NaL NaR ‘1’ ΔVTHNL ‘0’ NL NR L R CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  16. Parametric Yield CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  17. Parametric Yield CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  18. Parametric Yield CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  19. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  20. Conclusions • SB – SI Method: • accurate and fast • 6T SRAM DRV: • 45nm: DRV = 47%VDDnom; 16nm: DRV = 75.5%VDDnom • 6T SRAM Parametric Yield • @T = 2ns, DRV = 500mV • 45nm: Y = 99.85%, 16nm: Y = 55.88% CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

  21. Thanks for your attention! CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

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