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Detector Data Link (DDL)

Detector Data Link (DDL). DDL hardware Csaba SOOS. S ource I nterface U nit. D estination I nterface U nit. R ead O ut R eceiver C ard. L ocal D ata C oncentrator. Readout system. Front-end electronics. P2 Cavern. DDL SIU. D etector D ata L inks. Optical Fibre ~200 meters.

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Detector Data Link (DDL)

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  1. Detector Data Link (DDL) DDL hardware Csaba SOOS DDL hardware, DATE training

  2. Source Interface Unit Destination Interface Unit Read Out Receiver Card Local Data Concentrator Readout system Front-end electronics P2 Cavern DDL SIU Detector Data Links Optical Fibre ~200 meters P2 Access shaft DDL DIU RORC Front- End Digital Crate/Computer LDC DDL hardware, DATE training

  3. DDL architecture • Source Interface Unit (SIU) (1) • Interface to the Front-end Electronics (2) • Destination Interface Unit (DIU) (3) • Interface to the Readout Receiver Card (4) • Full duplex optical link (5) • Multimode optical cable of up to 200 m 1 3 5 2 4 DDL hardware, DATE training

  4. DDL hardware DDL hardware, DATE training

  5. DDL interfaces • SIU-FEE interface • 3.3V (LVTTL) interface • 32-bit wide half-duplex data bus (bi-directional bus) • Bi-directional flow control • User defined clock (synchronous interface) • JTAG interface • DIU-RORC interface • 3.3V (LVTTL) interface • 32-bit wide full-duplex data bus • Bi-directional flow control • User defined clock (synchronous interface) DDL hardware, DATE training

  6. SIU-FEE interface fbD(31..0) - data lines (bi-directional) fbTEN_N - data enable (bi-directional) fbCTRL_N - data qualifier (bi-directional) fiDIR - bus direction (FEE input) fiBEN_N - bus enable (FEE input) fiLF_N - link full (FEE input) foBSY_N - front-end busy (SIU input) foCLK - interface clock (SIU input) TAP_TCK - JTAG clock (FEE input) TAP_TDI - JTAG data in (FEE input) TAP_TDO - JTAG data out (SIU input) TAP_TMS - JTAG mode select (FEE input) TAP_TRST - JTAG reset (FEE input) DDL hardware, DATE training

  7. DIU-RORC interface riD(31..0) - data lines (RORC input) riTEN_N - transfer enable (RORC input) riSTS_N - data qualifier (RORC input) riLF_N - link full (RORC input) riLD_N - link down (RORC input) roD(31..0) - data lines (DIU input) roTEN_N - transfer enable (DIU input) roCMD_N - data qualifier (DIU input) roBSY_N - RORC busy (DIU input) roRST_N - DIU reset (DIU input) roCLK - interface clock (DIU input) DDL hardware, DATE training

  8. Link management RORC DIU SIU idle Power-on Reset SIU reset Power-on SIU reset off-line off-line Offline Offline on-line on-line Online on-line Online on-line Link up DDL hardware, DATE training

  9. RORC DIU SIU FEE on-line on-line Online Online FEE command foCLK FECTRL fiBEN_N idle fiDIR FEE control FECTRL fbD fbTEN_N CTSTW fbCTRL_N Report on-line on-line Front-end control DDL hardware, DATE training

  10. RORC DIU SIU FEE on-line on-line Online Online FEE command foCLK foCLK FECTRL fiBEN_N fiBEN_N on-line fiDIR fiDIR FEE status read FESTRD FESTW HiZ HiZ HiZ fbD fbD HiZ HiZ HiZ FESTW fbTEN_N fbTEN_N HiZ HiZ HiZ fbCTRL_N fbCTRL_N CTSTW Status and report on-line on-line Front-end status read DDL hardware, DATE training

  11. RORC DIU SIU FEE on-line on-line Online Online FEE command foCLK foCLK foCLK foCLK foCLK RDYRX EOBTR fiBEN_N fiBEN_N fiBEN_N fiBEN_N fiBEN_N fiDIR fiDIR fiDIR fiDIR fiDIR RDYRX min. 16 cycles D0 RDYRX EOBTR Dn-1 Dn-1 HiZ Dn Dn HiZ FESTW D1 FESTW D2 D4 HiZ D0 D5 HiZ data blocks fbD fbD fbD fbD fbD Report FEE data HiZ HiZ HiZ HiZ CTSTW fbTEN_N fbTEN_N fbTEN_N fbTEN_N fbTEN_N Event data Flow control HiZ HiZ HiZ fbCTRL_N fbCTRL_N fbCTRL_N fbCTRL_N fbCTRL_N HiZ CTSTW FEE command fiLF_N fiLF_N fiLF_N EOBTR Report Event read DDL hardware, DATE training

  12. RORC DIU SIU FEE on-line on-line Online Online FEE command foCLK foCLK STBWR fiBEN_N fiBEN_N fiDIR fiDIR STBWR Block data data block D0 Dn-1 STBWR Dn D1 D2 EOBTR D4 D5 fbD fbD Report FEE data CTSTW fbTEN_N fbTEN_N Flow control fbCTRL_N fbCTRL_N CTSTW FEE command EOBTR foBSY_N foBSY_N EOBTR Report Block write DDL hardware, DATE training

  13. RORC DIU SIU FEE on-line on-line Online Online FEE command foCLK foCLK foCLK foCLK STBRD EOBTR fiBEN_N fiBEN_N fiBEN_N fiBEN_N fiDIR fiDIR fiDIR fiDIR STBRD D0 STBRD EOBTR HiZ Dn-1 Dn HiZ D1 FESTW D2 D4 HiZ D5 HiZ data block fbD fbD fbD fbD Report FEE data HiZ HiZ HiZ HiZ CTSTW fbTEN_N fbTEN_N fbTEN_N fbTEN_N Block data Flow control HiZ HiZ HiZ fbCTRL_N fbCTRL_N fbCTRL_N fbCTRL_N HiZ CTSTW FEE command fiLF_N fiLF_N EOBTR Report Block read DDL hardware, DATE training

  14. PCI RORC DDL hardware, DATE training

  15. D-RORC DDL hardware, DATE training

  16. RORC features • Interface between the DIU and PCI local bus • pRORC: 32 bit/33 MHz PCI version, max. throughput 132MB/s • D-RORC: 64 bit/66 MHz PCI version, max. throughput 528MB/s • PCI master capability, data push architecture • Autonomous operation with little software assistance • Supports multi-paged memory management • Direct data transfer to the PC memory • No local memory on the board • Small elasticity buffers between different clock domains • Built-in test capability • Internal pattern generator can produce formatted data DDL hardware, DATE training

  17. PRORC PC memory bank The Free FIFO Firmware Free FIFO page address page address page address PC CPU readout Allocation of free pages DDL hardware, DATE training

  18. PRORC PC memory bank Direct Memory Access DDL Firmware PC CPU No involvement DDL hardware, DATE training

  19. PRORC PC memory bank page status page status page status address address address The Ready FIFO DDL Firmware Ready FIFO PC CPU readout Delivery of filled pages DDL hardware, DATE training

  20. Test equipments • Front-end Emulator Interface Card (FEIC) • Fully functional hardware to emulate the detector front-ends • Formatted data block generation • Internal (free running) or external (pulse) triggering capabilities • Adjustable parameters (using front-end control) • Operates at the nominal speed of the DDL • Source Interface Unit Simulator (SIMU) • Simulates the behavior of the DDL without any additional hardware • Eases the development and the hardware debugging • Size is similar to the real SIU DDL hardware, DATE training

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