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CPE 626 The SystemC Language. Aleksandar Milenkovic E-mail: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka. Outline. Writing testbenches SystemC types Arrays Resolved Logic Vector Clocks. Test Benches. Creating test benches
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CPE 626 The SystemC Language Aleksandar Milenkovic E-mail: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka
Outline • Writing testbenches • SystemC types • Arrays • Resolved Logic Vector • Clocks A. Milenkovic
Test Benches • Creating test benches • one process to generate stimulus, the other one to test results • stimulus are generated in the main program, another process test the results • generated and testing are both done in the main program • Typical approach A. Milenkovic
Example: Counter // Filename : count.h #include "systemc.h" SC_MODULE(count) { sc_in<bool> load; sc_in<int> din; sc_in<bool> clock; // input ports sc_out<int> dout; // output port int count_val; // internal data st. void count_up(); SC_CTOR(count) { SC_METHOD(count_up); // Method proc. // Sensitive to Rising edge clock sensitive_pos << clock; } }; // Filename : count.cpp #include "count.h" void count::count_up() { if (load) { count_val = din; } else { // Read/Write of local storage count_val = count_val + 1; } // Write to Output port dout = count_val; } A. Milenkovic
Example: Testbench for Counter // count_stim.cc #include "count_stim.h" void count_stim::stimgen() { while (true) { load = true; // load 0 din = 0; wait(); // count up, value = 1 load = false; wait(); // count up, value = 2 wait(); // count up, value = 3 wait(); // count up, value = 4 wait(); // count up, value = 5 wait(); // count up, value = 6 wait(); // count up, value = 7 } } #include "systemc.h" SC_MODULE(count_stim) { sc_out<bool> load; sc_out<int> din; // input port sc_in<bool> clock; // input port sc_in<int> dout; void stimgen(); SC_CTOR(count_stim) { SC_THREAD(stimgen); sensitive_pos (clock); } }; A. Milenkovic
Example: Main #include "count.h" #include "count_stim.h" #include "display.h" int sc_main(int argc, char* argv[]) { sc_signal<bool> LOAD; sc_signal<int> DIN, DOUT; // clock sc_clock CLOCK("clock", 20); int sim_time = 0; if (argc==2) sim_time = atoi(argv[1]); if (sim_time==0) sim_time = 1000; count u_count ("count"); u_count.load(LOAD); u_count.din(DIN); u_count.dout(DOUT); u_count.clock(CLOCK); count_stim u_count_stim("count_stim"); u_count_stim.load(LOAD); u_count_stim.din(DIN); u_count_stim.dout(DOUT); u_count_stim.clock(CLOCK); display u_display("display"); u_display.dout(DOUT); sc_initialize(); sc_start(sim_time); return(0); } A. Milenkovic
SystemC Types • SystemC programs may use any C++ type along with any of the built-in ones for modeling systems • long, int, char, short, float, double • SystemC Built-in Types • sc_bit (0, 1), sc_logic (0, 1, X, Z) • Two- and four-valued single bit A. Milenkovic
SystemC Types • SystemC Built-in Types • sc_int<n>, sc_unint<n> • 1 to 64-bit signed and unsigned integers • sc_bigint<n>, sc_biguint<n> • arbitrary (fixed) width signed and unsigned integers • sc_bv, sc_lv • arbitrary width two- and four-valued vectors • sc_fixed, sc_ufixed • signed and unsigned fixed point numbers • User defined constructs A. Milenkovic
Read&Writing ports Use read() or write() methods, or Use assignment operator Ports, Reading&Writing ports sc_in<porttype> // input port of type porttype sc_out<porttype> // output port of type porttype sc_inout<porttype> // inout port of type porttype porttype may be any of the types discussed A. Milenkovic
Arrays sc_in<sc_logic> a[32]; // creates ports a[0] to a[31] // of type sc_logic sc_signal<sc_logic> i[16]; // creates signals i[0] to // i[15] of type sc_logic A. Milenkovic
Resolved Logic Vector • More than one driver is driving a signal Resolved logic vector port: sc_in_rv<n> x; //input resolved logic vector n bits wide sc_out_rv<n> y;// output resolved logic vector n bits wide sc_inout_rv<n> z; // inout resolved logic vector n bits wide A. Milenkovic
Resolved Vector Signals • Used to connect resolved logic vector ports Resolved logic vector signal: sc_signal_rv<n> sig3; // resolved logic vector signal // n bits wide A. Milenkovic
Clocks • Create clock object named clock1 • clock period is 20 time units • duty cycle is 50% • first edge will occur at 2 time units • first value will be true sc_clock clock1("clock1", 20, 0.5, 2, true); A. Milenkovic