300 likes | 565 Views
CPE 626 CPU Resources: Adders & Multipliers. Aleksandar Milenkovic E-mail: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka. Outline. Full Adder Ripple Carry Adder Carry-Look-Ahead Adder Manchester Adders Carry Select Adder Carry Skip Adder Conditional Sum Adder
E N D
CPE 626 CPU Resources:Adders & Multipliers Aleksandar Milenkovic E-mail: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka
Outline • Full Adder • Ripple Carry Adder • Carry-Look-Ahead Adder • Manchester Adders • Carry Select Adder • Carry Skip Adder • Conditional Sum Adder • Hybrid Designs
Full Adder • Inputs • data inputs A, B • carry in Cin • Outputs • sum S • carry out Cout
Transmission-Gate Adder (1) • A = 1 => -A = 0 => TG is open => out = -B • A = 0 => -A = 1 => TG is closed => out = B • A = 1 => -A = 0 => TG is closed => out = B • A = 0 => -A = 1 => TG is open => out = -B TG XOR TG XNOR
Ripple Carry Adder - RCA (1) • Method 1 • G[i] = A[i]*B[i] • P[i] = A[i]B[i] • C[i] = G[i] + P[i]*C[i-1] • S[i] = P[i] C[i-1] • Method 2 • G[i] = A[i]*B[i] • P[i] = A[i] + B[i] • C[i] = G[i] + P[i]*C[i-1] • S[i] = A[i]B[i]C[i-1]
Ripple Carry Adder - RCA (2) • Replace AND-OR pair with fast 2-inputs NAND gates RCA delay is proportional to n and is limited by the propagation of the carry signal through all of the stages
Ripple Carry Adder - RCA (3) Used in odd stages! Used in even stages!
Ripple Carry Adder - RCA (4) • Carry equations • C[i+1] = A[i]*B[i] + P[i]*C[i]orC[i+1] = (A[i] + B[i])*(P[i]’ + C[i])P[i]’ = NOT(P[i]) • Even stages • C1[i+1]’ = P[i]*C3[i]*C4[i] • C2[i+1] = A[i] + B[i] • C[i+1] = C1[i]*C2[i] • Odd stages • C3[i+1]’ = P[i]*C1[i]*C2[i] • C4[i+1]’ = A[i]*B[i] • C[i+1] = C3[i]’ + C4[i]’ • Inputs to stage zero:C3[0] = C4[0] = ‘0’
Carry-Look-Ahead Adder – CLA (1) • Idea: speed up carry computation – Ci+1 = Gi + Pi*Ci • Propagate: Pi = Ai + Bi • if Pi = 1, then carry from (i-1)th stage is propagated • Generate: Gi = Ai*Bi • if Gi = 1 there is carry out
Carry-Look-Ahead Adder – CLA (3) Domino implementation (Dynamic Carry Gates)
Brent-Kung CLA • a) lookahead terms • b) CLG cell • c) cells can be rearranged into tree • d) simplified representations for part a) • e) simplified representation for part c) • f) lookahead logic for 8-bit adder • g) Brent-Kung adder Reduces delay, increases the regularity, reduces the number of unnecessary switching events (power)
Manchester Adder Circuits (2) Static Stage Dynamic Stage MUX stage
Carry Select Adder (1) Compute 2 versions of the addition with different carry-ins, one assuming that the carry-in is 0 and another assuming that it is 1
Carry Skip Adder: Motivation Computing P3-0 is much simpler than computing G0-3 Let’s compute only P3-0!
Carry Skip Adder Practical only if the carry-in signals can be easily cleared at the start of each operation – e.g. precharging CMOS Carries begin rippling simultaneously through each block; If any block generates a carry, then the carry out will be true, even the carry-in may not be not true yet. If at the start of each add operation the carry-in to each block is 0, then correct carry-outs will be generated – carry-out can be thought of as if it is the G signal
Carry Skip Adder: Analysis • Assume • it takes 1 time unit for signal to propagate through two logic level • n bits wide adder • blocks of size k • It will take k units for a carry to ripple through a block of size k • Critical path • k units for the first block • n/k – 2 units to skip the blocks • k units to ripple through the last block • Increase the efficiency by varying the blocks size • 20 bits (4, 4, 4, 4, 4,): Delay = 4 + 3 + 4 = 11 • 20 bits (2, 5, 6, 5, 2): Delay = 9
Hybrid Designs: An Example • Combine CLA (Carry Look-Ahead) with RCA