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TRD geometry in CBMroot and conclusions for detector module design

TRD geometry in CBMroot and conclusions for detector module design. David Emschermann Institut für K ernphysik Universität Münster. Outline. the TRD layout in CBMroot Dec09 signal extraction from the TRD modules quadratic chambers and their rotations pad structure inside the modules

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TRD geometry in CBMroot and conclusions for detector module design

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  1. TRD geometry in CBMrootand conclusions for detector module design David Emschermann Institut für Kernphysik Universität Münster

  2. Outline • the TRD layout in CBMroot Dec09 • signal extraction from the TRD modules • quadratic chambers and their rotations • pad structure inside the modules • pad hit rates • arrangement of FEBs on the modules • dual sided MWPC prototypes • layout of TRD modules in TRD1 layer 1 • summary and outlook

  3. The TRD in CBMroot • 3 stations a 4 layers, 12 layers total TRD • positions in z: • station 1 - 5,1mstation 2 – 7,4m • station 3 – 9,6m • 1110 m² surface • 1,2million channels

  4. 2D readout dual MWPC, central PP 3D readout single MWPC, with 50% drift 3D readout single MWPC, with 33% drift Signal extraction and rates thickness (12 mm) 3 3 3 3 3 3 6 4 4 4 Data flow A A A A A A D A A D 1 time unit 3 time units 2,6 time units timing 100 kHz/cm² 30 kHz/cm² ? 40 kHz/cm² ? rate At fixed gas thickness, can we build detectors with a thin drift volume for hit rates below ~30 kHz/cm²?

  5. Choice of detector technology • In CBMroot we assume the following: • the TRD surface is divided into • quadratic modules • the modules allow for signal readout • perpendicular to the pad plane

  6. S size A module with 1 cm² pad size 50 cm 92 x 23 pads (5 x 20 mm)

  7. Station 1 – CBMroot Dec09 Approximate size of pads in cm² Approximate border of 30 kHz/cm² particle rate 8x S + 12x M + 36x L sized chambers in each layer

  8. Station 2 – CBMroot Dec09 8x S + 12x M + 80x L sized chambers in each layer

  9. Station 3 – CBMroot Dec09 144x L sized chambers in each layer

  10. Quadratic detector modules • We build quadratic detectors in 3 different sizes: • 50 cm x 50 cm – Small size chambers • 75 cm x 75 cm – Medium size chambers • 100 cm x 100 cm – Large size chambers • Use rectangular pads with fixed width of 5 mm • allowing a fixed chip-chip spacing on the FEBs • Scale the pad size by variing the pad length • Rotate the chambers by 90° between layers • to obtain 2D position information • Odd layers (1,3) with vertical pads • Even layers (2,4) with horizontal pads

  11. Rotating the modules – pad view 5mm x 20mm pads vertical pads horizontal pads odd layers (1,3) even layers (2,4)

  12. Detail of modules (S size) layer 1 layer 2 A chamber can contain pads of different sizes, here 5mm x 15mm (green) and 5mm x 20mm (yellow).

  13. Station 1 - hits per pad Based on interpolated data from the TSR. Cyrano Bermann Scale the pad size to yield 100 kHz hits per pad maximum.

  14. Station 2 - hits per pad Cyrano Bermann

  15. Station 3 - hits per pad size 66% scaled Cyrano Bermann

  16. Chip count for Dec09 geometry • for the full CBM TRD in Dec09 layout • 81984x 16 channel ASICs or • 41552x 32 channel ASICs S size 92 pads 2 2 32 channels / chip 2 2 24 channels / chip 2 2 16 channels / chip • some channels are lost at the two ends of each row • => need to optimise channels/chip for all detectors

  17. Channels per chip L size 192 pads 32 channels / chip – 16 cm chip spacing 24 channels / chip – 12 cm chip spacing 16 channels / chip – 8 cm chip spacing • with upcoming 5 mm pad width layout the • chambers have 92, 142 or 192 pads per row • pad number not always even multiple of 16 or 32

  18. Positioning front-end boards • the neighbor hit trigger requires data exchange • between ajacent pads (ASICs) • it therefore makes sense to place chips reading • pads of the same row on the same FEB • due to fixed pad width (5 mm) there is a common • chip-to-chip spacing for all TRD chambers • there is too little space on chambers with small • pads to place the FEBs parallel to the pad plane

  19. FEB size and arrangement • what will be the size of • the chip carriers? • what will be the width • of the FEBs? • vertical orientation of • the FEBs allows for • higher density of chips • data collection from and • distribution to FEBs is • possible on dedicated • buses: • slow control bus (blue) • optical readout bus (red)

  20. Detector back-panel chamber with 1cm² pads • the bus bar length scales with the pad length of the different detector chamber types • interface board design • with standard layout • decoupled from the • chamber geometry station 1 layer 1

  21. FEB communication • optical readout board (ORB, red) • detector control board (DCB, blue) • can act as interface to the outside

  22. ORB and DCB Zoom on FEB spacing for chambers with 40 mm pad length

  23. Dual sided MWPCs - pictures MuBu: Münster- Bucharest

  24. MuBu prototype chambers • can stand high rates, tested at 100k hits/cm²/s • central pad plane with double-sided MWPC • But: • signal extraction possible only in plane (2D) • at maximum 2 pad rows in one module • resulting in modules with large aspect ratio • geometrical acceptance only 66% with 1cm² pads

  25. The “real size” TRD prototype TRD station 1 pads too large: (4cm²) beam hole is too small: only 12cm x 5cm need a realistic TRD geometry

  26. MuBu module modifications • Following modifications are required to fit the • MuBu chambers into the CBMroot geometry: • assume two rows of pads in one detector module • use 5mm wide rectangular pads • scale pad size 1 cm², 2 cm², 4 cm², 8 cm² … • resulting in different width of modules • extend the module length from 36 cm to 50 cm • group the modules into quadratic segments • rotate segments between even and odd layers • for good position resolution on both dimensions

  27. Layer 1 – vertical pads Dual MWPCs in TRD1 – layer 1 1cm² 50 cm pad size 2cm² 48x/24x chambers - 1cm²/2cm² pads

  28. Layer 2 – horizontal pads Dual MWPCs in TRD1 – layer 2 quadratic segments rotated 48x/24x chambers - 1cm²/2cm² pads

  29. Staggered arrangement • Staggered arrangement of dual sided MWPCs • 8 quadratic => 72 rectangular modules • 576 MuBu modules in TRD1 and TRD2 • thickness of each layer increases by a factor 2 • electronics on front- and back-side of layers

  30. Detailed view of detectors MWPCs with 2 rows of 1cm² pads MWPCs with 2 rows of 2cm² pads • full coverage of the active area - many extra frames • same number of pads as with quadratical chambers

  31. Summary & Outlook • Dual sided MWPCs could cover 2% of the total • TRD surface (in the inner part of TRD1 and TRD2) • For the remaining 98% of the TRD, we need • to find a solution and build large area prototypes • We need to settle the chamber technology • (rate capability vs signal extraction, drift region?) • Tests of chambers with realistic dimensions and • pad size are needed. Limiting factors are the • anode wire length, pad plane PCB size.

  32. Thank you

  33. Backup

  34. With a pad width of the order of 5 mm a particle track will induce signals on 3 adjacent pads. The pad sizes vary in the range of : 5mm x 20mm = 100 mm² ~ 5 pF 5mm x 200mm = 1000 mm² ~ 25 pF Comparable ALICE TRD pads: 6,35mm x 90mm = 571,5 mm² ~ 15-20 pF Giving rise to the above estimated pad capacities for ideal wiretraces (+50% variation is easily possible). Is this input capacitance variation worth noting during the ASIC design? Pad sizes & pad capacity

  35. Layer 1 – vertical pads Dual MWPCs in the center – L1 48x/24x chambers - 1cm²/2cm² pads

  36. Layer 2 – horizontal pads Dual MWPCs in the center – L2 48x/24x chambers - 1cm²/2cm² pads

  37. Staggered detectors

  38. Rectangular prototype

  39. Simulations and data rates As input to the data rate estimation MC was provided by Elena for different collision energies, up to 35 GeV. The data rate estimations agree very well between the different input MC sets. We assume 3 firing pads per particle track @ 5mm pad width. 132 Bits raw data are generated by a 1 channel hit. (Timm) Then 100 kHz hit rate per pad are equal to 40 MBit/s data rate.

  40. Station 1 Layer 1 Bits/pad 1 MBit

  41. Station 1 Layer 2 Bits/pad 1 MBit

  42. Station 1 Layer 3 Bits/pad 1 MBit

  43. Station 1 Layer 4 Bits/pad 1 MBit

  44. Station 2 Layer 1 Bits/pad 1 MBit

  45. Station 2 Layer 2 Bits/pad 1 MBit

  46. Station 2 Layer 3 Bits/pad 1 MBit

  47. Station 2 Layer 4 Bits/pad 1 MBit

  48. Station 3 Layer 1 Bits/pad 1 MBit

  49. Station 3 Layer 2 Bits/pad 1 MBit

  50. Station 3 Layer 3 Bits/pad 1 MBit

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