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Power/Thermal Impact of Network Computing Cisco Router Technology Symposium

Power/Thermal Impact of Network Computing Cisco Router Technology Symposium. Evaldo Miranda & Laurence McGarry. Data Flow == Power / Thermal Flow. Source : Intel – 2003 Spring IDF. “Moore’s Law” on Processor Power. Source : Intel Technology Journal, Vol 6, Issue 2.

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Power/Thermal Impact of Network Computing Cisco Router Technology Symposium

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  1. Power/Thermal Impact of Network ComputingCisco Router Technology Symposium Evaldo Miranda & Laurence McGarry

  2. Data Flow == Power / Thermal Flow Source : Intel – 2003 Spring IDF

  3. “Moore’s Law” on Processor Power Source : Intel Technology Journal, Vol 6, Issue 2

  4. Source : Kenneth Goodson, Stanford University

  5. The Power Supply Chain 100% -5% -20% (Cooling) Generation Source Transmission Data Center ~55% - Electrical Pwr ~30% - Processing Pwr -10% DC-DC -10% AC/DC Application Load; Processor, DSP, Memory Graphics Line Card Shelf/Rack System

  6. Total Cost of Ownership

  7. Trends for Power Power Delivery & Utilization for Analog Processing Pipeline ADC “Digital calibration“ removes D/A and linear gain error by adjusting digital weights [Karanicolas, 1993] Redundancy (RSD arithmetic) helps tolerate large sub A/D errors [Lewis, 1987] • ADC bottleneck: fast & highly linear gain element. • 50-70% of total pipeline ADC power is consumed by interstage amplifiers

  8. Precision Amplifier Trends for Power Power Delivery & Utilization for Analog Processing “Open loop“ • Lower Noise • Increased Signal Range • Lower Power • Faster • Nonlinear • Signal Processing used to linearize! [Murmann 03] : Open-Loop Amplification

  9. Trends for Power Power Delivery & Utilization for Analog Processing [Iroga/Murmann] : Digital Nonlinearity Compensation

  10. Trends for Power Power Delivery & Utilization for Analog Processing Stage1 Power Breakdown 16X 4X [Iroga/Murmann 05] : 12-b, 75-MS/s ADC implemented in 0.35um CMOS

  11. Trends for Power • Moore’s Law is different for Analog and Digital • The area of digital is cut in half with every new generation • The area of analog is reduced by 20~30% with every new generation • The cost of digital is cut in half every 2~3 years • The cost of analog is cut in half every 4~8 years Ref: Anton Bakker - Analog Devices Inc.

  12. Layout comparison in 0.25um CMOS Trends for Power Bondpad + ESD 12-bit ADC 10pF

  13. Pwr Losses V V V T T T T PWM REF Fault / OK Buck Converter I Supply Computing Load

  14. Pwr Losses PWM DPWM Buck Converter II V V V T T T Supply T Computing Load REF Fault / OK Monitor - Control - Adapt

  15. Battery Chargers VRM for PCs Drivers POL Switchers LDO Secondary-Side Controller & Sync Rect I2C/SMBus Hot Swap Sequencers Margining Micro-Controller Power Management Units Temp Sensor & Fan Controllers Smart Power Chain Block Diagram SMBus / SST / PMBus Switch Bridge LC Filter OrFET Rectifier Rectifier& PFC Drivers PFC Ctrl PWM Delivering Power Through Information

  16. Summary and Conclusions • Proliferation of computing/networking/communications applications resulting in extreme and bounded power density demands on supporting devices/systems • Falling cost of digital technology allows availability of digital techniques to optimize/improve system functions • Adaptable/reconfigurable regulators for efficient energy transfer • Utilize information about the source & load • Use System level management USE YOUR “BUCK” CONVERTER EFFICIENTLY

  17. Presented By:Evaldo Martins MirandaPower & Thermal Design ManagerLaurence McGarryPower & Thermal Marketing Manager Analog Devices, Inc. 3550 North First St San Jose – CA 95134 evaldo.miranda@analog.com Laurence.mcgarry@analog.com

  18. Back-up

  19. Power/Thermal Impact of Network Computing • Growth of fixed and mobile devices linked by a network processing voice, data and video. • Moore’s law on Power and Thermals from processors to buildings for data centers • Demand for power and cooling capacity on existing data centers and server farms. • Power Management in Processors • Fab processes (eg: strained silicon and low leakage oxides) • Device structure (eg: 3D devices) • Circuit designs (eg: voltage, frequency and body switching) • Architecture (eg: multi-core and intelligent timing/scheduling/multi-tasking) • Power Management for Computing Platforms (HW Board level and Systems) • Increase efficiency of passive devices and their use: Drivers, FETs, Inductors (coupled) • Improve Thermal solutions: bigger heat sinks, fans, heat–pipes and liquid cooling • Use Multi-phase Voltage Regulator up to 130A per processor w/ up to 20kW per rack • Multiple power rails • Power Management Opportunities (Platform Systems Solutions) • Remote Monitoring/Control of networked systems • Balancing computing load & data handling traffic • Security & Virtualization • Rethinking Power Conversion (+ Communication) • Increase efficiency/utilization/reliability of platforms/racks & Reduce cooling • Efficiency under varying load, ambient and fault conditions while reducing component count and adjusting for component aging, degradation and failure prediction.

  20. Pentium 4 Thermal Solution

  21. Redundant Server Power Supply 12V@50A (600W)

  22. Pwr Losses V V V T T T Buck Converter I Supply Computing Load PWM REF Fault / OK

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